与DSP通信时，RD&WR信号

 

///////////////////////////////////////////////////////////
reg  [ 1:0]  rd,wr;
reg   [15:0] dsp_data_out;
assign DSP_D = (DSP_WE && !DSP_RD) ? dsp_data_out:16'hzzzz;

// Below is the communication with DSP.
//  
always @( posedge DSP_CLKOUT)
begin
    // help to find the time of falling or rising edge.
    {rd[1],rd[0]} = {rd[0],DSP_RD};
    {wr[1],wr[0]} = {wr[0],DSP_WE};
    
    if(!XZCS0)begin
        if( rd == 'b10 ) // read
            case( DSP_A )
                /* axis1 */
                `AXIS1_BASE + `FFRP_ADDR: dsp_data_out <= ffrp;
                `AXIS1_BASE + `FFWP_ADDR: dsp_data_out <= ffwp[1];

                default:    dsp_data_out <= DSP_A;
                
           endcase
        else if ( wr == 'b01 ) // write 
            case( DSP_A )
                /* axis1 */
              
                `AXIS1_BASE + `FFWP_ADDR: if( EALLOW == 'b1 )  ffwp[1] <= DSP_D;   // EALLOW protected.                
                
                default:    ;
            endcase
    end// if(!XZCS0)begin
end