摘要： module handshack( input clk, input rst_n, input req, input [7:0] datain, output ack, output [7:0] dataout);reg reqr1,reqr2,reqr3;reg [7:0] dataoutr;reg ackr;always @ (posedge clk,negedge rst_n)if(!rst_n) {reqr3,reqr2,reqr1} <= 3'b111;else {reqr3,reqr2,reqr1} <= {reqr2,reqr1,r... 阅读全文