FPGA Prototyping By Verilog Examples第五章 状态机FSM设计
摘要：
上升沿检测电路之Moore型FSM// Listing 5.3module edge_detect_moore ( input wire clk, reset, input wire level, output reg tick ); // symbolic state declaration localparam [1:0] zero = 2'b00, edg = 2'b01, one = 2'b10; // signal declaration reg [1:0] state_reg, state_next; // state register always @(p 阅读全文
posted @ 2011-04-12 11:04 齐威王 阅读(1192) 评论(0) 推荐(1) 编辑