FPGA Prototyping By Verilog Examples第三章
摘要：
// Listing 3.1module eq1_always ( input wire i0, i1, output reg eq // eq declared as reg ); // p0 and p1 declared as reg reg p0, p1; always @(i0, i1) // i0 an i1 must be in sensitivity list begin // the order of statements is important p0 = ~i0 & ~i1; p1 = i0 & i1; eq = p0 | p1; endendmodule 阅读全文
posted @ 2011-04-08 11:45 齐威王 阅读(1077) 评论(0) 推荐(0) 编辑