线性移位寄存器LFSR电路设计

module LFSR 
(
    input clk,
    input rst_n,
    output out
);

reg [9:0] q=10'b1010101010;
wire tap = q[2]^q[9];
assign out = q[9];

always @ (posedge clk,negedge rst_n)
if(!rst_n)
    q <= 10'b1010101010;
else
    q <= {q[8:0],tap};
endmodule

将LFSR赋初始值1010101010，最低为q0=q2 xor  q9,输出为最高位q9;

测试程序如下：

`timescale 1 ns/1 ns
module LFSR_tb();

localparam  T=20; // clock period   

reg 	clk,rst_n;
wire	out;

LFSR LFSR_tb
(
	.clk(clk),
	.rst_n(rst_n),
	.out(out)
);


always 
begin
	clk = 1'b1;
	#(T/2);
	clk = 1'b0;
	#(T/2);
end

initial
begin
	rst_n	= 1'b1;
	#(T/2);
	rst_n	= 1'b1;
	#(100*T);
	$stop;
end

endmodule

功能和时序仿真结果如下：

测试文件如下：

`timescale 1 ns/1 ns
module LFSR_tb();

localparam  T=20; // clock period   

reg 	clk,rst_n;
wire	out;

LFSR LFSR_tb
(
	.clk(clk),
	.rst_n(rst_n),
	.out(out)
);


always 
begin
	clk = 1'b1;
	#(T/2);
	clk = 1'b0;
	#(T/2);
end

initial
begin
	rst_n	= 1'b0;
	#(T/2);
	rst_n	= 1'b1;
	#(100*T);
	$stop;
end

endmodule

功能和时序仿真如下：