FPGA流水灯
使用Verilog语言实现8个led流水灯,源码如下:
module led_test(
input clk, //50MHz
input reset_n,
output reg [7:0] led //output 8 leds
);
reg [31:0] cnt; //计数
always@(posedge clk or negedge reset_n) begin
if(!reset_n)
cnt <= 32'b0;
else if(cnt == 25_000_000-1)
cnt <= 32'b0;
else
cnt <= cnt + 1;
end
always@(posedge clk or negedge reset_n) begin
if(!reset_n)
led <= 8'hfe; //引脚输出低电平有效
else if(cnt == 25_000_000-1) //计时500ms
led <= {led[6:0],led[7]}; //拼接符实现位移寄存器功能
else
led <= led;
end
endmodule
时序图就不放了,在Quartus中绑定引脚后下载sof文件可以观察到led灯依次点亮。