展锐SE8451E 开启硬件流控

Dear Customer：如电话沟通，若将uart0配置成3M波特率，需进行如下更改：
1、时钟源更改为96M
/sprdroid10_trunk_19c_rls1/bsp/kernel/kernel4.14/arch/arm/boot/dts/sl8541e.dtsi

 574 &uart1 {
575     clock-names = "enable", "uart", "source";
576     clocks = <&apapb_gate CLK_UART1_EB>,
577 --          <&ap_clk CLK_UART1>, <&ext_26m>;
    ++           <&ap_clk CLK_UART1>, <&pll CLK_TWPLL_96M>;
578 };

2、开启硬件流控
/sprdroid10_trunk_19c_rls1/bsp/bootloader/u-boot15/board/spreadtrum/sl8541e_1h10/pinmap-sl8541e.c

 94--  {REG_PIN_U0CTS,                         BITS_PIN_AF(3)},
95--  {REG_MISC_PIN_U0CTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},
96--  {REG_PIN_U0RTS,                         BITS_PIN_AF(3)},
97--  {REG_MISC_PIN_U0RTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},
94++  {REG_PIN_U0CTS,                         BITS_PIN_AF(0)},
95++  {REG_MISC_PIN_U0CTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},
96++  {REG_PIN_U0RTS,                         BITS_PIN_AF(0)},
97++  {REG_MISC_PIN_U0RTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},
==== State: Opened by: sunsea on 09 October 2021 16:10:38 ====
 
Dear Engineer：
Uart1（ttyS1）的时钟配置如下：
&uart1 {
    clock-names = "enable", "uart", "source";
    clocks = <&apapb_gate CLK_UART1_EB>,
         <&ap_clk CLK_UART1>, <&ext_26m>;

posted @ 2022-07-16 18:40 PYPYN 阅读(495) 评论(0) 编辑收藏举报

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	574 &uart1 {
	575 clock-names = "enable", "uart", "source";
	576 clocks = <&apapb_gate CLK_UART1_EB>,
	577 -- <&ap_clk CLK_UART1>, <&ext_26m>;
	++ <&ap_clk CLK_UART1>, <&pll CLK_TWPLL_96M>;
	578 };

	94-- {REG_PIN_U0CTS, BITS_PIN_AF(3)},
	95-- {REG_MISC_PIN_U0CTS, BITS_PIN_DS(1)\|BIT_PIN_NULL\|BIT_PIN_WPD\|BIT_PIN_SLP_AP\|BIT_PIN_SLP_WPD\|BIT_PIN_SLP_Z},
	96-- {REG_PIN_U0RTS, BITS_PIN_AF(3)},
	97-- {REG_MISC_PIN_U0RTS, BITS_PIN_DS(1)\|BIT_PIN_NULL\|BIT_PIN_NUL\|BIT_PIN_SLP_AP\|BIT_PIN_SLP_NUL\|BIT_PIN_SLP_OE},

	94++ {REG_PIN_U0CTS, BITS_PIN_AF(0)},
	95++ {REG_MISC_PIN_U0CTS, BITS_PIN_DS(1)\|BIT_PIN_NULL\|BIT_PIN_WPU\|BIT_PIN_SLP_AP\|BIT_PIN_SLP_WPU\|BIT_PIN_SLP_IE},
	96++ {REG_PIN_U0RTS, BITS_PIN_AF(0)},
	97++ {REG_MISC_PIN_U0RTS, BITS_PIN_DS(1)\|BIT_PIN_NULL\|BIT_PIN_NUL\|BIT_PIN_SLP_AP\|BIT_PIN_SLP_NUL\|BIT_PIN_SLP_OE},

	==== State: Opened by: sunsea on 09 October 2021 16:10:38 ====

	Dear Engineer：
	Uart1（ttyS1）的时钟配置如下：
	&uart1 {
	clock-names = "enable", "uart", "source";
	clocks = <&apapb_gate CLK_UART1_EB>,
	<&ap_clk CLK_UART1>, <&ext_26m>;