收集于.COM 缺氧®（张亚峰）的博客的一点小知识

1. 用“与”操作实现快速求余运算，例如:
a = a % 8;
可以改为：
a = a & 7;
说明：位操作只需要一个指令周期即可完成，而大部分的C编译器的“%”运算均是调用子程序来完成的，代码长、执行速度慢。通常，只要是求2n方的余数，均可使用位操作的方法来代替。

2.优缺点latch & Flip-Flop:
-->Latch takes less area, consume less power, facilitate time borrowing or cycle stealing, not friendly with DFT tools
-->Flip-flop takes more area, consumes more power, allow synchronous logic, friendly with DFT tools

3.Difference between “==” and “===” operators:

The “==” are synthesizable while “===” operators are not synthesizable. If either of the operand in “==” has x or z the the result is always x while “===” compare x and z too. The same is true for “!=” and “!==” operators.

4.General Reusable coding practices
    Register all the outputs of critical design blocks
    Avoid path that traces through number of hierarchies and then return back to same hierarchy
    Partition the design based on functional goals and the clock domains
    Avoid instantiating technology specific modules
    Use parameters and declare them at the top with meaningful names
    Avoid internally generated clocks and resets
    Avoid glue logic at the top level

5.Common mistakes made in RTL code
    Module with input but no outputs: It will synthesize into no logic since there is no output.
    Inferring latch: It is very common for synthesis tool to infer latch due to incomplete if-else statement. Also, incomplete case statement or missing default in case statement also generates latches. The designers must be very careful while write RTL code for if-else or case blocks.
    Combinatorial timing loops: These loops are created when output of combinatorial logic or gate is fed back to its input making a timing loop. This kind of loops unnecessary increase the number of cycles by infinitely going around the circle in the same path. These loops also cause a problem in testability. Most of the lint tools can detect these loops much early in design phase.
    Incomplete sensitivity list in always block: It is important to have complete sensitivity list in always block for combinatorial logic such as multiplexer. The verilog-2001, provide a very clean solution by just typing the following statement instead of typing all the inputs in the sensitivity list. This will ensure that, the latches are not inferred for combinatorial logic.

6.Design for Testability
    Factors affecting testability
        Presence of tri-state logic
        Gated clock for Flip-flop
        Internally generated clock and reset
        Reset derived by output of another flip-flop
        Presence of latches

    Avoid tri-state bus: The synthesis tools do not like tri-state buses and there are not testable. If you have to use tri-sate buses then to ensure testability, pass the enable of the tri-state bus through AND gate so that scan_enable signal can control the tri-state bus.
    Derived Reset: To avoid losing any data in scan mode, add “OR” gate before the signal reach the reset of next Flip-flip. Add “scan_enable” signal to the other input of the “OR” gate. In test mode, asserting “sacn_enable” make sure that the asynchronous reset is disabled.
    Derived clock: Use multiplexer logic at the output of the derived clock before it fed to the input of another flip-flip. Make the other input of mux as the primary clock and the select line as “scan_enable”. This will make sure that the primary clock is used during testability.
    Gated clock: It is a very common practice for power sensitive designs. You basically disable the complete block by simply disabling the input clock by using AND gate. To ensure the design is testable, add OR gate after the AND gate and add scan_enable as another input to the OR gate in addition to the output to the AND gate.
    Presence of latches: Since enable signal to latch is not a regular clock that is fed to the rest of the logic. To ensure testability, you need to use OR gate using “enable” and “scan_enable” signals as input and fed the output to the enable port of the latch.

1. 用“与”操作实现快速求余运算，例如:

?

1	a = a % 8;

可以改为：

?

1	a = a & 7;

说明：位操作只需要一个指令周期即可完成，而大部分的C编译器的“%”运算均是调用子程序来完成的，代码长、执行速度慢。通常，只要是求2n方的余数，均可使用位操作的方法来代替。