MULTITHREADING AND CHIP MULTIPROCESSORS

COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE NINTH EDITION

 

The most important measure of performance for a processor is the rate at which it
executes instructions. This can be expressed as
MIPS rate = f
*
IPC
where f is the processor clock frequency, in MHz, and IPC (instructions per cycle)
is the average number of instructions executed per cycle. Accordingly, designers
have pursued the goal of increased performance on two fronts: increasing clock fre-
quency and increasing the number of instructions executed or, more properly, the
number of instructions that complete during a processor cycle. As we have seen in
earlier chapters, designers have increased IPC by using an instruction pipeline and
then by using multiple parallel instruction pipelines in a superscalar architecture.
With pipelined and multiple-pipeline designs, the principal problem is to maximize
the utilization of each pipeline stage. To improve throughput, designers have cre-
ated ever more complex mechanisms, such as executing some instructions in a dif-
ferent order from the way they occur in the instruction stream and beginning execu-
tion of instructions that may never be needed. But as was discussed in Section 2.2,
this approach may be reaching a limit due to complexity and power consumption
concerns.
An alternative approach, which allows for a high degree of instruction-level
parallelism without increasing circuit complexity or power consumption, is called
multithreading. In essence, the instruction stream is divided into several smaller
streams, known as threads, such that the threads can be executed in parallel.
The variety of specific multithreading designs, realized in both commercial
systems and experimental systems, is vast. In this section, we give a brief survey of
the major concepts.