model checker
https://jyywiki.cn/OS/2022/slides/4.slides#/3/1
Model Checker
Model checking is a method for formally verifying finite-state systems——只要能为系统建立模型，就能用 prove by brute-force 证明正确/找到错误。
Model checker 的一切就是状态机！
- Safety: 红色的状态不可到达
- G(V, E)G(V,E) 上的可达性问题
- (Strong) Liveness: 从任意状态出发，都能到达绿/蓝色状态
- G(V, E)G(V,E) 上的什么问题？
- 如何展示这个状态机？
- 如何能避免无效的探索？
更多的 Model Checker
真实程序的状态空间太大？
- Model checking for programming languages using VeriSoft (POPL'97, 第一个 “software model checker”)
- Finding and reproducing Heisenbugs in concurrent programs (OSDI'08, Small Scope Hypothesis 🪳🪳🪳)
- Using model checking to find serious file system errors (OSDI'04, Best Paper 🏅，可以用在不并发的系统上)
不满足于简单的内存模型？
- VSync: Push-button verification and optimization for synchronization primitives on weak memory models (ASPLOS'21, Distinguished Paper 🏅)
Model checking is a method for formally verifying finite-state concurrent systems. Specifications about the system are expressed as temporal logic formulas, and efficient symbolic algorithms are used to traverse the model defined by the system and check if the specification holds or not. Extremely large state-spaces can often be traversed in minutes. The technique has been applied to several complex industrial systems such as the Futurebus+ and the PCI local bus protocols. Here is an overview.
The Model Checking Group is part of the Specification and Verification Center at CMU
model checker
程序状态机的各种状态
【理解并发程序执行 (Peterson算法、模型检验与软件自动化工具) [南京大学2022操作系统-P4]】https://www.bilibili.com/video/BV15T4y1Q76V
inspect --- 检查对象
yeild checkpoint()
https://jyywiki.cn/OS/2022/slides/4.slides#/1/3
Model Checking at CMU https://www.cs.cmu.edu/~modelcheck/
