(筆記) 如何使用Debussy與ModelSim做Co-Simulation? (SOC) (Verilog) (VHDL) (Debussy) (ModelSim)
Abstract
本文介紹如何使用Debussy與ModelSim做Co-Simulation，並使用Verilog、VHDL以及Verilog搭配VHDL交叉一起simulation。
Introduction
使用環境：Debussy 5.4 v9 + ModelSim SE 6.3e
我之前一直使用Debussy + NC-Verilog做simulation，Debussy (Verdi)可以說是HDL的Source Insight，是trace與debug的神兵利器，NC-Verilog也是Verilog simulator中速度最快的，可是最近因工作需要，拿到的一包code卻是用Verilog寫RTL，用VHDL寫testbench，所以必須2種語言一起做simulation，我在NC-Verilog一直無法成功讓兩種語言一起simulation。ModelSim雖然支援Verilog + VHDL co-simulation，但用慣Debussy的我還是無法忘懷其方便的trace code方式，所以若能讓ModelSim也能dump出Debussy所需要的fsdb檔案，這樣就太完美了。
接下來會分4個方式討論
1.RTL與testbench皆使用Verilog
2.RTL與testbench皆使用VHDL
3.RTL使用VHDL，testbench使用Verilog
4.RTL使用Verilog，testbench使用VHDL
1.RTL與testbench皆使用Verilog
Step 1：
設定ModeSim使用Verilog PLI (因為testbench使用Verilog)
將C:\Novas\Debussy\share\PLI\modelsim_pli\WINNT\novas.dll複製到C:\Modeltech_6.3e\win32\下
修改C:\Modeltech_6.3e\modelsim.ini，將Veriuser部分修改成如下所示：
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; use by verilog
Veriuser = novas.dll
; use by vhdl
; Veriuser = novas_fli.dll
modelsim.ini是個read only檔，要修改前記得修改其屬性才能存檔。
Step 2：
RTL部分 (以4 bit counter為例)
counter.v / Verilog
1 /*
2 (C) OOMusou 2011 http://oomusou.cnblogs.com
3
4 Filename : counter.v
5 Simulator : ModelSim 6.3e, Debussy 5.4 v9
6 Description : ModelSim with debussy
7 Release : 01/31/2010 1.0
8 */
9
10 module counter (
11 clk,
12 rst_n,
13 cnt
14 );
15
16 input clk;
17 input rst_n;
18 output [3:0] cnt;
19
20 reg [3:0] cnt;
21
22 always@(posedge clk, negedge rst_n) begin
23 if (~rst_n)
24 cnt <= 4'h0;
25 else
26 cnt <= cnt + 1'b1;
27 end
28
29 endmodule
Step 3：
Testbench部分
counter_tb.v / Verilog
1 /*
2 (C) OOMusou 2011 http://oomusou.cnblogs.com
3
4 Filename : counter_tb.v
5 Compiler : ModelSim 6.3e, Debussy 5.4 v9
6 Description : ModelSim with debussy
7 Release : 01/31/2010 1.0
8 */
9
10 module counter_tb;
11
12 reg clk;
13 reg rst_n;
14 wire [3:0] cnt;
15
16 // 50MHz
17 always #(10) clk = ~clk;
18
19 initial begin
20 #0;
21 clk = 1'b0;
22 rst_n = 1'b0;
23
24 #5;
25 rst_n = 1'b1;
26 #195;
27 $finish;
28 end
29
30 initial begin
31 $fsdbDumpfile("counter.fsdb");
32 $fsdbDumpvars(0, counter_tb);
33 end
34
35 counter u_counter (
36 .clk(clk),
37 .rst_n(rst_n),
38 .cnt(cnt)
39 );
40
41 endmodule
19行
initial begin
#0;
clk = 1'b0;
rst_n = 1'b0;
#5;
rst_n = 1'b1;
#195;
$finish;
end
一搬來說，若在NC-Verilog做simulation，我們會在testbench內指定結束simulation的時間，不過在ModelSim裡，simulation時間是由ModelSim script控制，在testbench內寫$finish並沒有用，所以會省略$finish時間入下。
initial begin
#0;
clk = 1'b0;
rst_n = 1'b0;
#5;
rst_n = 1'b1;
end
Step 4：
ModelSim script部分
vsim.do
vlib work
vlog counter.v
vlog counter_tb.v
vsim counter_tb
run 200ns
q
其中
vlib work
建立work library。
vlog counter.v
vlog counter_tb.v
編譯RTL：counter.v 與 testbench：counter_tb.v，vlog為modelsim的Verilog compiler。
vsim counter_tb
以counter_tb為top module進行simulation。
run 200ns
命令ModelSim執行200 ns的simulation。
q
離開ModelSim
Step 5：
執行ModelSim的批次檔
mod.bat
vsim -c -do sim.do
-c 表示ModelSim將以console mode執行，因為在Debussy + ModelSim時，只把ModelSim當成NC-Verilog使用，並沒有用到ModelSim的GUI模式。
-do 表示執行ModelSim script。
執行結果
D:\0Clare\VerilogLab\ModelSim\counter_verilog>vsim -c -do sim.do
Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl
# 6.3e
# do sim.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008
# -- Compiling module counter
#
# Top level modules:
# counter
# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008
# -- Compiling module counter_tb
#
# Top level modules:
# counter_tb
# vsim counter_tb
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading C:\Modeltech_6.3e\win32/novas.dll
# // ModelSim SE 6.3e Feb 2 2008
# //
# // Copyright 1991-2008 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading work.counter_tb(fast)
# Loading work.counter(fast)
# Novas FSDB Dumper for ModelSim, Release 5.4v9 (Win95/NT) 05/04/2005
# Copyright (C) 1996 - 2004 by Novas Software, Inc.
# *Novas* Create FSDB file 'counter.fsdb'
# *Novas* Start dumping the scope(counter_tb), layer(0).
# *Novas* End of dumping.
# ** Note: $finish : counter_tb.v(27)
# Time: 200 ns Iteration: 0 Instance: /counter_tb
Step 6：
執行Debussy批次檔部份
deb.bat
debussy -2001 counter_tb.v counter.v -ssf counter.fsdb -sswr counter.rc
-2001表示支援Verilog 2001語法
-ssf 載入Debussy dump file
-sswr 載入Debussy signal file
執行結果
2.RTL與testbench皆使用VHDL
Step 1：
設定ModelSim使用VHDL FLI (因為testbench使用VHDL)
將C:\Novas\Debussy\share\PLI\modelsim_fli54\WINNT\novas_fli.dll複製到C:\Modeltech_6.3e\win32\下
修改C:\Modeltech_6.3e\modelsim.ini，將Veriuser部分修改成如下所示：
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; use by verilog
;Veriuser = novas.dll
; use by vhdl
Veriuser = novas_fli.dll
modelsim.ini是個read only檔，要修改前記得修改其屬性才能存檔。
複製C:\Novas\Debussy\share\PLI\modelsim_fli54\WINNT\novas.vhd到自己的project底下
(為什麼Verilog不需要這個檔，而VHDL需要這個檔，稍後會解釋)
Step 2：
RTL部分 (以4 bit counter為例)
counter.vhd / VHDL
1 -- (C) OOMusou 2011 http://oomusou.cnblogs.com
2
3 -- Filename : counter.vhd
4 -- Simulator : ModelSim 6.3e, Debussy 5.4 v9
5 -- Description : ModelSim with debussy
6 -- Release : 02/05/2011 1.0
7
8 library IEEE;
9 use IEEE.std_logic_1164.all;
10 use IEEE.std_logic_unsigned.all;
11
12 entity counter is
13 port ( clk : in std_logic;
14 rst_n : in std_logic;
15 cnt : out std_logic_vector(3 downto 0));
16 end entity counter;
17
18 architecture arc of counter is
19 signal cnt_r : std_logic_vector(3 downto 0);
20 begin
21 process(clk, rst_n)
22 begin
23 if (rst_n = '0') then
24 cnt_r <= "0000";
25 elsif rising_edge(clk) then
26 cnt_r <= cnt_r + 1;
27 end if;
28 end process;
29
30 cnt <= cnt_r;
31 end arc;
Step 3：
Testbench部分
counter.vhd / VHDL
1 -- (C) OOMusou 2011 http://oomusou.cnblogs.com
2
3 -- Filename : counter_tb.vhd
4 -- Simulator : ModelSim 6.3e, Debussy 5.4 v9
5 -- Description : ModelSim with debussy
6 -- Release : 01/31/2010 1.0
7
8 library IEEE;
9 use IEEE.std_logic_1164.all;
10 use IEEE.std_logic_unsigned.all;
11 use work.pkg.all;
12
13 entity counter_tb is
14 end entity counter_tb;
15
16 architecture arc of counter_tb is
17 component counter
18 port (
19 clk : in std_logic;
20 rst_n : in std_logic;
21 cnt : out std_logic_vector(3 downto 0)
22 );
23 end component;
24
25 signal clk : std_logic := '0';
26 signal rst_n : std_logic := '0';
27 signal cnt : std_logic_vector(3 downto 0);
28
29 begin
30 process
31 begin -- 50MHz
32 clk_loop : loop
33 clk <= '0';
34 wait for 10 ns;
35 clk <= '1';
36 wait for 10 ns;
37 end loop clk_loop;
38 end process;
39
40 process
41 begin
42 wait for 5 ns;
43 rst_n <= '1';
44 end process;
45
46 process
47 begin
48 fsdbDumpfile("counter.fsdb");
49 fsdbDumpvars(0, "counter_tb");
50 wait;
51 end process;
52
53 u_counter : counter
54 port map (
55 clk => clk,
56 rst_n => rst_n,
57 cnt => cnt
58 );
59 end arc;
11行
use work.pkg.all;
這是因為novas.vhd與VHDL FLI的原因，稍後會解釋。
47行
process
begin
fsdbDumpfile("counter.fsdb");
fsdbDumpvars(0, "counter_tb");
wait;
end process;
一樣使用fsdbDumpfile()與fsdbDumpvars()兩個Debussy所提供的函數，不過在VHDL FLI並不需要如Verilog PLI一樣加上$。
wait也一定要加上，否則在ModelSim做simulation時會造成無窮回圈無法停止。
Step 4：
ModelSim script部分
vsim.do
vlib work
vcom novas.vhd
vcom counter.vhd
vcom counter_tb.vhd
vsim counter_tb
run 200ns
q
因為是VHDL，所以全部改用vcom編譯。
其中novas.vhd是從Debussy目錄複製過來的，為什麼需要編譯這個檔案呢?
VHDL FLI (Foreign Language Interface)與Verilog PLI (Programming Language Interface)不同的地方在於，當你自己提供由C寫的function給simulator使用時，Verilog PLI會自己到所提供的dll去找是否有此function，但VHDL FLI需要自己去提供mapping的動作，告訴simulator哪一個function對應dll內那ㄧ個function，novas.vhd就是提供這個mapping的腳色。
若直接使用Debussy所提供的novas.vhd，在執行ModelSim會有以下錯誤訊息。
# ** Warning: (vsim-FLI-3159) Failed to find foreign function 'fliparseVariableInFile' in FLI object file "C:\Modeltech_6.3e\win32/./novas_fli.dll".
意思是novas.vhd定義的fliparseVariableInFile在novas_fli.dll找不到，致於為什麼會有此錯誤，我並不清楚。
將novas.vhd修改成如下所示：
novas.vhd / VHDL
1 package pkg is
2 attribute foreign : string;
3
4 procedure fsdbDumpfile (file_name : in string);
5 attribute foreign of fsdbDumpfile : procedure is "fliparseTraceInit ./novas_fli.dll";
6
7 procedure fsdbDumpvars (depth : in integer;
8 region_name : in string);
9 attribute foreign of fsdbDumpvars : procedure is "fliparsePartial ./novas_fli.dll";
10 end;
11
12 package body pkg is
13 procedure fsdbDumpfile(file_name : in string) is
14 begin
15 assert false report "ERROR : foreign subprogram not called" severity note;
16 end;
17
18 procedure fsdbDumpvars(depth : in integer;
19 region_name : in string) is
20 begin
21 assert false report "ERROR : foreign subprogram not called" severity note;
22 end;
23 end;
24
25 entity novas is end;
26
27 architecture novas_arch of novas is
28 attribute foreign : string;
29 attribute foreign of novas_arch : architecture is "fliparseCommand novas_fli.dll";
30 begin
31 end;
32
也就是僅留下fsdbDumpfile()與fsdbDumpvars()兩個function，其他的都刪除。
根據我使用Debussy的經驗，只要留這兩個function就夠用了，其他Debussy的function我還真的沒用過。
在novas.vhd也看到了這些是定義在pkg這個package下，所以在counter_tb.vhd必須use work.pkg.all。
Step 5：
執行ModelSim的批次檔
mod.bat
vsim -c -do sim.do
執行結果
D:\0Clare\VerilogLab\ModelSim\counter_vhdl>vsim -c -do sim.do
Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl
# 6.3e
# do sim.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008
# -- Loading package standard
# -- Compiling package pkg
# -- Compiling package body pkg
# -- Loading package pkg
# -- Compiling entity novas
# -- Compiling architecture novas_arch of novas
# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity counter
# -- Compiling architecture arc of counter
# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package pkg
# -- Compiling entity counter_tb
# -- Compiling architecture arc of counter_tb
# vsim counter_tb
# Loading C:\Modeltech_6.3e\win32/novas.dll
# // ModelSim SE 6.3e Feb 2 2008
# //
# // Copyright 1991-2008 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.pkg(body)
# Loading C:\Modeltech_6.3e\win32/./novas_fli.dll
# Loading work.counter_tb(arc)
# Loading work.counter(arc)
# Novas FSDB Dumper for ModelSim 5.4 (FLI), Release 5.4v9 (Win95/NT) 05/04/2005
# Copyright (C) 1996 - 2004 by Novas Software, Inc.
# *Novas* Create FSDB file 'counter.fsdb'
Step 6：
執行Debussy批次檔部份
deb.bat
debussy –vhdl –93 novas.vhd counter_tb.vhd counter.vhd –top counter_tb -ssf counter.fsdb -sswr counter.rc
-vhdl 表示支援VHDL語法，因為Debussy預設支援Verilog
-93 表示支援VHDL 93的語法
-top 指定top module，在Verilog可以不指定top，Debussy可以自動判斷而抓到top module，但是VHDL沒辦法，需要自己指定，若不指定，待會會有GUI要你手動挑選top module
執行結果
3.RTL使用VHDL，testbench使用Verilog
Step 1：
設定ModeSim使用Verilog PLI (因為testbench使用Verilog)
將C:\Novas\Debussy\share\PLI\modelsim_pli\WINNT\novas.dll複製到C:\Modeltech_6.3e\win32\下
修改C:\Modeltech_6.3e\modelsim.ini，將Veriuser部分修改成如下所示：
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; use by verilog
Veriuser = novas.dll
; use by vhdl
; Veriuser = novas_fli.dll
modelsim.ini是個read only檔，要修改前記得修改其屬性才能存檔。
Step 2：
RTL部分 (以4 bit counter為例)
counter.vhd / VHDL
1 -- (C) OOMusou 2011 http://oomusou.cnblogs.com
2
3 -- Filename : counter.vhd
4 -- Simulator : ModelSim 6.3e, Debussy 5.4 v9
5 -- Description : ModelSim with debussy
6 -- Release : 02/05/2011 1.0
7
8 library IEEE;
9 use IEEE.std_logic_1164.all;
10 use IEEE.std_logic_unsigned.all;
11
12 entity counter is
13 port ( clk : in std_logic;
14 rst_n : in std_logic;
15 cnt : out std_logic_vector(3 downto 0));
16 end entity counter;
17
18 architecture arc of counter is
19 signal cnt_r : std_logic_vector(3 downto 0);
20 begin
21 process(clk, rst_n)
22 begin
23 if (rst_n = '0') then
24 cnt_r <= "0000";
25 elsif rising_edge(clk) then
26 cnt_r <= cnt_r + 1;
27 end if;
28 end process;
29
30 cnt <= cnt_r;
31 end arc;
Step 3：
Testbench部分
counter_tb.v / Verilog
1 /*
2 (C) OOMusou 2011 http://oomusou.cnblogs.com
3
4 Filename : counter_tb.v
5 Compiler : ModelSim 6.3e, Debussy 5.4 v9
6 Description : ModelSim with debussy
7 Release : 01/31/2010 1.0
8 */
9
10 module counter_tb;
11
12 reg clk;
13 reg rst_n;
14 wire [3:0] cnt;
15
16 // 50MHz
17 always #(10) clk = ~clk;
18
19 initial begin
20 #0;
21 clk = 1'b0;
22 rst_n = 1'b0;
23
24 #5;
25 rst_n = 1'b1;
26 #195;
27 $finish;
28 end
29
30 initial begin
31 $fsdbDumpfile("counter.fsdb");
32 $fsdbDumpvars(1, counter_tb);
33 end
34
35 counter u_counter (
36 .clk(clk),
37 .rst_n(rst_n),
38 .cnt(cnt)
39 );
40
41 endmodule
30行
initial begin
$fsdbDumpfile("counter.fsdb");
$fsdbDumpvars(1, counter_tb);
end
$fsdbDumpvars()的第一個參數是填1不是0，若填0會產生以下warning，不過並不影響最後fsdb的結果。
# ** Warning: Unknown scope type: counter_tb.u_counter 1010
# : counter_tb.v(30)
# Time: 0 ns Iteration: 0 Instance: /counter_tb
# ** Warning: Unknown scope type: counter_tb.u_counter 1010
# : counter_tb.v(30)
# Time: 0 ns Iteration: 0 Instance: /counter_tb
# *Novas* End of dumping.
Step 4：
ModelSim script部分
vsim.do
vlib work
vcom counter.vhd
vlog counter_tb.v
vsim counter_tb
run 200ns
q
VHDL使用vcom編譯，Verilog使用vlog編譯。
Step 5：
執行ModelSim的批次檔
mod.bat
vsim -c -do sim.do
執行結果
D:\0Clare\VerilogLab\ModelSim\counter_vhdl_verilog>vsim -c -do sim.do
Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl
# 6.3e
# do sim.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity counter
# -- Compiling architecture arc of counter
# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008
# -- Compiling module counter_tb
#
# Top level modules:
# counter_tb
# vsim counter_tb
# Loading C:\Modeltech_6.3e\win32/novas.dll
# // ModelSim SE 6.3e Feb 2 2008
# //
# // Copyright 1991-2008 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading work.counter_tb(fast)
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.counter(arc)
# Novas FSDB Dumper for ModelSim, Release 5.4v9 (Win95/NT) 05/04/2005
# Copyright (C) 1996 - 2004 by Novas Software, Inc.
# *Novas* Create FSDB file 'counter.fsdb'
# *Novas* Start dumping the scope(counter_tb), layer(0).
# ** Warning: Unknown scope type: counter_tb.u_counter 1010
# : counter_tb.v(30)
# Time: 0 ns Iteration: 0 Instance: /counter_tb
# ** Warning: Unknown scope type: counter_tb.u_counter 1010
# : counter_tb.v(30)
# Time: 0 ns Iteration: 0 Instance: /counter_tb
# *Novas* End of dumping.
D:\0Clare\VerilogLab\ModelSim\counter_vhdl_verilog>vsim -c -do sim.do
Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl
# 6.3e
# do sim.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity counter
# -- Compiling architecture arc of counter
# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008
# -- Compiling module counter_tb
#
# Top level modules:
# counter_tb
# vsim counter_tb
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading C:\Modeltech_6.3e\win32/novas.dll
# // ModelSim SE 6.3e Feb 2 2008
# //
# // Copyright 1991-2008 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading work.counter_tb(fast)
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.counter(arc)
# Novas FSDB Dumper for ModelSim, Release 5.4v9 (Win95/NT) 05/04/2005
# Copyright (C) 1996 - 2004 by Novas Software, Inc.
# *Novas* Create FSDB file 'counter.fsdb'
# *Novas* Start dumping the scope(counter_tb), layer(1).
# *Novas* End of dumping.
Step 6：
執行Debussy批次檔部份
deb.bat
vhdlcom -93 counter.vhd
vericom -2001 counter_tb.v
debussy -lib work -top counter_tb -ssf counter.fsdb -sswr counter.rc
若RTL與testbench同時包含Verilog與VHDL，Debussy就無法直接開啟，必須先將Verilog與VHDL分別編譯成lib，然後才可開啟。
VHDL使用vhdlcom作編譯，-93表示支援VHDL 93的語法，Verilog使用vericom作編譯，-2001表示支援Verilog 2001語法，vhdlcom與vericom預設都會編譯在work這個lib下，所以debussy開啟時需用-lib指定使用work這個lib，並用-top指定top module，這樣才可開啟mixed-language的design。
執行結果
4.RTL使用Verilog，testbench使用VHDL
Step 1：
設定ModelSim使用VHDL FLI (因為testbench使用VHDL)
將C:\Novas\Debussy\share\PLI\modelsim_fli54\WINNT\novas_fli.dll複製到C:\Modeltech_6.3e\win32\下
修改C:\Modeltech_6.3e\modelsim.ini，將Veriuser部分修改成如下所示：
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; use by verilog
;Veriuser = novas.dll
; use by vhdl
Veriuser = novas_fli.dll
modelsim.ini是個read only檔，要修改前記得修改其屬性才能存檔。
Step 2：
RTL部分 (以4 bit counter為例)
counter.v / Verilog
1 /*
2 (C) OOMusou 2011 http://oomusou.cnblogs.com
3
4 Filename : counter.v
5 Simulator : ModelSim 6.3e, Debussy 5.4 v9
6 Description : ModelSim with debussy
7 Release : 01/31/2010 1.0
8 */
9
10 module counter (
11 clk,
12 rst_n,
13 cnt
14 );
15
16 input clk;
17 input rst_n;
18 output [3:0] cnt;
19
20 reg [3:0] cnt;
21
22 always@(posedge clk, negedge rst_n) begin
23 if (~rst_n)
24 cnt <= 4'h0;
25 else
26 cnt <= cnt + 1'b1;
27 end
28
29 endmodule
Step 3：
Testbench部分
counter.vhd / VHDL
1 -- (C) OOMusou 2011 http://oomusou.cnblogs.com
2
3 -- Filename : counter_tb.vhd
4 -- Simulator : ModelSim 6.3e, Debussy 5.4 v9
5 -- Description : ModelSim with debussy
6 -- Release : 01/31/2010 1.0
7
8 library IEEE;
9 use IEEE.std_logic_1164.all;
10 use IEEE.std_logic_unsigned.all;
11 use work.pkg.all;
12
13 entity counter_tb is
14 end entity counter_tb;
15
16 architecture arc of counter_tb is
17 component counter
18 port (
19 clk : in std_logic;
20 rst_n : in std_logic;
21 cnt : out std_logic_vector(3 downto 0)
22 );
23 end component;
24
25 signal clk : std_logic := '0';
26 signal rst_n : std_logic := '0';
27 signal cnt : std_logic_vector(3 downto 0);
28
29 begin
30 process
31 begin -- 50MHz
32 clk_loop : loop
33 clk <= '0';
34 wait for 10 ns;
35 clk <= '1';
36 wait for 10 ns;
37 end loop clk_loop;
38 end process;
39
40 process
41 begin
42 wait for 5 ns;
43 rst_n <= '1';
44 end process;
45
46 process
47 begin
48 fsdbDumpfile("counter.fsdb");
49 fsdbDumpvars(0, "counter_tb");
50 wait;
51 end process;
52
53 u_counter : counter
54 port map (
55 clk => clk,
56 rst_n => rst_n,
57 cnt => cnt
58 );
59 end arc;
Step 4：
ModelSim script部分
vsim.do
vlib work
vcom novas.vhd
vlog counter.v
vcom counter_tb.vhd
vsim counter_tb
run 200ns
q
VHDL使用vcom編譯，Verilog使用vlog編譯。
Step 5：
執行ModelSim的批次檔
mod.bat
vsim -c -do sim.do
執行結果
D:\0Clare\VerilogLab\ModelSim\counter_verilog_vhdl>vsim -c -do sim.do
Reading C:/Modeltech_6.3e/tcl/vsim/pref.tcl
# 6.3e
# do sim.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008
# -- Loading package standard
# -- Compiling package pkg
# -- Compiling package body pkg
# -- Loading package pkg
# -- Compiling entity novas
# -- Compiling architecture novas_arch of novas
# Model Technology ModelSim SE vlog 6.3e Compiler 2008.02 Feb 2 2008
# -- Compiling module counter
#
# Top level modules:
# counter
# Model Technology ModelSim SE vcom 6.3e Compiler 2008.02 Feb 2 2008
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package pkg
# -- Compiling entity counter_tb
# -- Compiling architecture arc of counter_tb
# vsim counter_tb
# Loading C:\Modeltech_6.3e\win32/novas.dll
# // ModelSim SE 6.3e Feb 2 2008
# //
# // Copyright 1991-2008 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.pkg(body)
# Loading C:\Modeltech_6.3e\win32/./novas_fli.dll
# Loading work.counter_tb(arc)
# Loading work.counter(fast)
# Novas FSDB Dumper for ModelSim 5.4 (FLI), Release 5.4v9 (Win95/NT) 05/04/2005
# Copyright (C) 1996 - 2004 by Novas Software, Inc.
# *Novas* Create FSDB file 'counter.fsdb'
Step 6：
執行Debussy批次檔部份
deb.bat
vericom -2001 counter.v
vhdlcom -93 novas.vhd counter_tb.vhd
debussy -lib work -top counter_tb -ssf counter.fsdb -sswr counter.rc
執行結果
完整程式碼下載
counter_verilog.7z (RTL與testbench皆使用Verilog)
counter_vhdl.7z (RTL與testbench皆使用VHDL)
counter_vhdl_verilog.7z (RTL使用VHDL，testbench使用Verilog)
counter_verilog_vhdl.7z (RTL使用Verilog，testbench使用VHDL)
Conclusion
本文介紹了Debussy與ModelSim的Co-Simulation，這兩個工具的合作，可以發揮ModelSim能Verilog與VHDL一起simulation的優點，又可發揮Debussy的trace與debug的功力；並且實際示範了2種HDL語言交互simulation的方法，其中包含了一些小技巧。
在Quartus II也允許這種跨語言的方式作synthesis，或許你會問，為什麼要搞的這麼複雜?乖乖只用Verilog或只用VHDL就好了，但現實上，這兩個HDL語言佔有率幾乎一半一半，無論是工作上也好，或者看書網路上找資源，遇到Verilog或者VHDL的機會仍相當多，像我是Verilog比較熟，但有些IP是用VHDL開發(無論是買來的或者網路抓的)，所以VHDL也要多少懂一點，最少要能一起Co-Simulation，雖然重要的是硬體的設計，但多懂一種語言也不是壞事。
Reference
[1] 小時不識月 Stupid & Hungry, [筆記] 怎樣使用Debussy + ModelSim快速查訪前仿真波形
[2] 電子開發網, debussy和modelsim協同仿真 (VHDL)
全文完。
