(筆記) 什麼是handle? (SOC) (Verilog) (Verilog PLI)
Abstract
以前學Win32、MFC時,總是搞不清楚pointer、reference與handle的差異,Verilog PLI也有handle概念,在Verilog PLI Handbook 2nd P.60用了很簡單的一句話解釋了handle。
Introduction
A handle is not a pointer to the actual object, it is a pointer to information about the object.
Reference
The Verilog PLI Handbook 2nd, P.60