(筆記) 使用SignalTap II之前，只需Start Analysis & Elaboration即可 (SOC) (SignalTap II)

Abstract
一般我們在使用SignalTap II時，會在Quartus II做2次編譯，其實只需做1次編譯即可。

Introduction
在SignalTap II with Verilog Designs這篇paper，教我們在SigalTap II加入node前，要在Quartus II做一次編譯，加入node後，又要再做一次編譯，不過你我都知道Quartus II編譯實在要很久，能少一次編譯，就賺到一次時間。

在Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems這篇paper的p.5，有以下這段話：

Before you can connect the ELA to signals in your design, you must first compile the design to build the node database. For this step, you do not need to fit the design completely. The Start & Analysis & Elaboration command builds the node database, but stops before the fitting step.

也就是說，SignalTap II在加入node之前，只需知道有哪些node即可，還不需做fitter和assembler的動作，因此不需要做『Start Compilation』，只需做『Start Analysis & Elaboration』即可，等加完node，再做『Start Compilation』，這樣可以減少一次編譯的時間。

See Also
(原創) 如何使用SignalTap II觀察reg與wire值? (SOC) (Verilog) (Quartus II) (SignalTap II)

Reference
SignalTap II with Verilog Designs
Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems