(原創) 如何Real Time產生灰階影像? (SOC) (DE2-70) (TRDB-D5M)
本文討論如何在DE2-70平台實現。
Abstract
本文討論如何在DE2-70平台實現。
Introduction
使用環境：Quartus II 7.2 SP3 + DE2-70 (Cyclone II EP2C70F896C6N) + TRDB-D5M
在(原創) 如何Real Time產生灰階影像? (SOC) (DE2) (TRDB-DC2)，我們討論了real time產生灰階影像的原理架構，並在DE2平台實現，DE2-70與DE2有些許不同：
1.DE2-70提供兩顆32MB SDRAM做frame buffer。
2.DE2-70使用TRDB-D5M這個500萬像素CMOS。
3.DE2-70使用4.3寸800 x 480的LTM。
對於產生灰階影像來說，由於SDRAM與LTM的改變，所以實現上必須稍做調整。
Method 1：
在SDRAM之前
DE2_70.v / Verilog
1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : DE2_70.v
5 Compiler : Quartus II 7.2 SP3
6 Description : Demo how to use TRDB-D5M with LTM to make gray before SDRAM on DE2-70
7 Release : 08/23/2008 1.0
8 */
9
10 module DE2_70 (
11 //////////////////////// Clock Input ////////////////////////
12 input iCLK_28, // 28.63636 MHz
13 input iCLK_50, // 50 MHz
14 input iCLK_50_2, // 50 MHz
15 input iCLK_50_3, // 50 MHz
16 input iCLK_50_4, // 50 MHz
17 input iEXT_CLOCK, // External Clock
18 //////////////////////// Push Button ////////////////////////
19 input [3:0] iKEY, // Pushbutton[3:0]
20 //////////////////////// DPDT Switch ////////////////////////
21 input [17:0] iSW, // Toggle Switch[17:0]
22 //////////////////////// 7-SEG Dispaly ////////////////////////
23 output [6:0] oHEX0_D, // Seven Segment Digit 0
24 output oHEX0_DP, // Seven Segment Digit 0 decimal point
25 output [6:0] oHEX1_D, // Seven Segment Digit 1
26 output oHEX1_DP, // Seven Segment Digit 1 decimal point
27 output [6:0] oHEX2_D, // Seven Segment Digit 2
28 output oHEX2_DP, // Seven Segment Digit 2 decimal point
29 output [6:0] oHEX3_D, // Seven Segment Digit 3
30 output oHEX3_DP, // Seven Segment Digit 3 decimal point
31 output [6:0] oHEX4_D, // Seven Segment Digit 4
32 output oHEX4_DP, // Seven Segment Digit 4 decimal point
33 output [6:0] oHEX5_D, // Seven Segment Digit 5
34 output oHEX5_DP, // Seven Segment Digit 5 decimal point
35 output [6:0] oHEX6_D, // Seven Segment Digit 6
36 output oHEX6_DP, // Seven Segment Digit 6 decimal point
37 output [6:0] oHEX7_D, // Seven Segment Digit 7
38 output oHEX7_DP, // Seven Segment Digit 7 decimal point
39 //////////////////////////// LED ////////////////////////////
40 output [8:0] oLEDG, // LED Green[8:0]
41 output [17:0] oLEDR, // LED Red[17:0]
42 //////////////////////////// UART ////////////////////////////
43 output oUART_TXD, // UART Transmitter
44 input iUART_RXD, // UART Receiver
45 output oUART_CTS, // UART Clear To Send
46 input iUART_RTS, // UART Requst To Send
47 //////////////////////////// IRDA ////////////////////////////
48 output oIRDA_TXD, // IRDA Transmitter
49 input iIRDA_RXD, // IRDA Receiver
50 /////////////////////// SDRAM Interface ////////////////////////
51 inout [31:0] DRAM_DQ, // SDRAM Data bus 32 Bits
52 output [12:0] oDRAM0_A, // SDRAM0 Address bus 13 Bits
53 output [12:0] oDRAM1_A, // SDRAM1 Address bus 13 Bits
54 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
55 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
56 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
57 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
58 output oDRAM0_WE_N, // SDRAM0 Write Enable
59 output oDRAM1_WE_N, // SDRAM1 Write Enable
60 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
61 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
62 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
63 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
64 output oDRAM0_CS_N, // SDRAM0 Chip Select
65 output oDRAM1_CS_N, // SDRAM1 Chip Select
66 output [1:0] oDRAM0_BA, // SDRAM0 Bank Address
67 output [1:0] oDRAM1_BA, // SDRAM1 Bank Address
68 output oDRAM0_CLK, // SDRAM0 Clock
69 output oDRAM1_CLK, // SDRAM1 Clock
70 output oDRAM0_CKE, // SDRAM0 Clock Enable
71 output oDRAM1_CKE, // SDRAM1 Clock Enable
72 //////////////////////// Flash Interface ////////////////////////
73 inout [14:0] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
74 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
75 output [21:0] oFLASH_A, // FLASH Address bus 26 Bits
76 output oFLASH_WE_N, // FLASH Write Enable
77 output oFLASH_RST_N, // FLASH Reset
78 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
79 input iFLASH_RY_N, // FLASH Ready/Busy output
80 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
81 output oFLASH_OE_N, // FLASH Output Enable
82 output oFLASH_CE_N, // FLASH Chip Enable
83 //////////////////////// SRAM Interface ////////////////////////
84 inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
85 inout [3:0] SRAM_DPA, // SRAM Parity Data Bus
86 output [18:0] oSRAM_A, // SRAM Address bus 21 Bits
87 output oSRAM_ADSC_N, // SRAM Controller Address Status
88 output oSRAM_ADSP_N, // SRAM Processor Address Status
89 output oSRAM_ADV_N, // SRAM Burst Address Advance
90 output [3:0] oSRAM_BE_N, // SRAM Byte Write Enable
91 output oSRAM_CE1_N, // SRAM Chip Enable
92 output oSRAM_CE2, // SRAM Chip Enable
93 output oSRAM_CE3_N, // SRAM Chip Enable
94 output oSRAM_CLK, // SRAM Clock
95 output oSRAM_GW_N, // SRAM Global Write Enable
96 output oSRAM_OE_N, // SRAM Output Enable
97 output oSRAM_WE_N, // SRAM Write Enable
98 //////////////////// ISP1362 Interface ////////////////////////
99 inout [15:0] OTG_D, // ISP1362 Data bus 16 Bits
100 output [1:0] oOTG_A, // ISP1362 Address 2 Bits
101 output oOTG_CS_N, // ISP1362 Chip Select
102 output oOTG_OE_N, // ISP1362 Read
103 output oOTG_WE_N, // ISP1362 Write
104 output oOTG_RESET_N, // ISP1362 Reset
105 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
106 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
107 input iOTG_INT0, // ISP1362 Interrupt 0
108 input iOTG_INT1, // ISP1362 Interrupt 1
109 input iOTG_DREQ0, // ISP1362 DMA Request 0
110 input iOTG_DREQ1, // ISP1362 DMA Request 1
111 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
112 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
113 //////////////////// LCD Module 16X2 ////////////////////////////
114 inout [7:0] LCD_D, // LCD Data bus 8 bits
115 output oLCD_ON, // LCD Power ON/OFF
116 output oLCD_BLON, // LCD Back Light ON/OFF
117 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
118 output oLCD_EN, // LCD Enable
119 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
120 //////////////////// SD Card Interface ////////////////////////
121 inout SD_DAT, // SD Card Data
122 inout SD_DAT3, // SD Card Data 3
123 inout SD_CMD, // SD Card Command Signal
124 output oSD_CLK, // SD Card Clock
125 //////////////////////// I2C ////////////////////////////////
126 inout I2C_SDAT, // I2C Data
127 output oI2C_SCLK, // I2C Clock
128 //////////////////////// PS2 ////////////////////////////////
129 inout PS2_KBDAT, // PS2 Keyboard Data
130 inout PS2_KBCLK, // PS2 Keyboard Clock
131 inout PS2_MSDAT, // PS2 Mouse Data
132 inout PS2_MSCLK, // PS2 Mouse Clock
133 //////////////////////// VGA ////////////////////////////
134 output oVGA_CLOCK, // VGA Clock
135 output oVGA_HS, // VGA H_SYNC
136 output oVGA_VS, // VGA V_SYNC
137 output oVGA_BLANK_N, // VGA BLANK
138 output oVGA_SYNC_N, // VGA SYNC
139 output [9:0] oVGA_R, // VGA Red[9:0]
140 output [9:0] oVGA_G, // VGA Green[9:0]
141 output [9:0] oVGA_B, // VGA Blue[9:0]
142 //////////////// Ethernet Interface ////////////////////////////
143 inout [15:0] ENET_D, // DM9000A DATA bus 16Bits
144 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
145 output oENET_CS_N, // DM9000A Chip Select
146 output oENET_IOW_N, // DM9000A Write
147 output oENET_IOR_N, // DM9000A Read
148 output oENET_RESET_N, // DM9000A Reset
149 input iENET_INT, // DM9000A Interrupt
150 output oENET_CLK, // DM9000A Clock 25 MHz
151 //////////////////// Audio CODEC ////////////////////////////
152 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
153 input iAUD_ADCDAT, // Audio CODEC ADC Data
154 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
155 output oAUD_DACDAT, // Audio CODEC DAC Data
156 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
157 output oAUD_XCK, // Audio CODEC Chip Clock
158 //////////////////// TV Devoder ////////////////////////////
159 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
160 input [7:0] iTD1_D, // TV Decoder1 Data bus 8 bits
161 input iTD1_HS, // TV Decoder1 H_SYNC
162 input iTD1_VS, // TV Decoder1 V_SYNC
163 output oTD1_RESET_N, // TV Decoder1 Reset
164 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
165 input [7:0] iTD2_D, // TV Decoder2 Data bus 8 bits
166 input iTD2_HS, // TV Decoder2 H_SYNC
167 input iTD2_VS, // TV Decoder2 V_SYNC
168 output oTD2_RESET_N, // TV Decoder2 Reset
169 //////////////////////// GPIO ////////////////////////////////
170 inout [31:0] GPIO_0, // GPIO Connection 0 I/O
171 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
172 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
173 inout GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
174 inout GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
175 inout [31:0] GPIO_1, // GPIO Connection 1 I/O
176 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
177 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
178 inout GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
179 inout GPIO_CLKOUT_P1 // GPIO Connection 1 Clock Output 1
180 );
181
182 // CCD
183 wire [11:0] CCD_DATA;
184 wire CCD_SDAT;
185 wire CCD_SCLK;
186 wire CCD_FLASH;
187 wire CCD_FVAL;
188 wire CCD_LVAL;
189 wire CCD_PIXCLK;
190 wire CCD_MCLK; // CCD Master Clock
191
192 wire [15:0] Read_DATA1;
193 wire [15:0] Read_DATA2;
194 wire VGA_CTRL_CLK;
195 wire [11:0] mCCD_DATA;
196 wire mCCD_DVAL;
197 wire mCCD_DVAL_d;
198 wire [15:0] X_Cont;
199 wire [15:0] Y_Cont;
200 wire [9:0] X_ADDR;
201 wire [31:0] Frame_Cont;
202 wire DLY_RST_0;
203 wire DLY_RST_1;
204 wire DLY_RST_2;
205 wire Read;
206 reg [11:0] rCCD_DATA;
207 reg rCCD_LVAL;
208 reg rCCD_FVAL;
209 wire [11:0] sCCD_R;
210 wire [11:0] sCCD_G;
211 wire [11:0] sCCD_B;
212 wire sCCD_DVAL;
213 reg [1:0] rClk;
214 wire sdram_ctrl_clk;
215
216 // Touch panel signal
217 wire [7:0] ltm_r; // LTM Red Data 8 Bits
218 wire [7:0] ltm_g; // LTM Green Data 8 Bits
219 wire [7:0] ltm_b; // LTM Blue Data 8 Bits
220 wire ltm_nclk; // LTM Clcok
221 wire ltm_hd;
222 wire ltm_vd;
223 wire ltm_den;
224 wire adc_dclk;
225 wire adc_cs;
226 wire adc_penirq_n;
227 wire adc_busy;
228 wire adc_din;
229 wire adc_dout;
230 wire adc_ltm_sclk;
231 wire ltm_grst;
232
233 // LTM Config
234 wire ltm_sclk;
235 wire ltm_sda;
236 wire ltm_scen;
237 wire ltm_3wirebusy_n;
238
239 assign CCD_DATA[0] = GPIO_1[11];
240 assign CCD_DATA[1] = GPIO_1[10];
241 assign CCD_DATA[2] = GPIO_1[9];
242 assign CCD_DATA[3] = GPIO_1[8];
243 assign CCD_DATA[4] = GPIO_1[7];
244 assign CCD_DATA[5] = GPIO_1[6];
245 assign CCD_DATA[6] = GPIO_1[5];
246 assign CCD_DATA[7] = GPIO_1[4];
247 assign CCD_DATA[8] = GPIO_1[3];
248 assign CCD_DATA[9] = GPIO_1[2];
249 assign CCD_DATA[10] = GPIO_1[1];
250 assign CCD_DATA[11] = GPIO_1[0];
251 assign GPIO_CLKOUT_N1 = CCD_MCLK;
252 assign CCD_FVAL = GPIO_1[18];
253 assign CCD_LVAL = GPIO_1[17];
254 assign CCD_PIXCLK = GPIO_CLKIN_N1;
255 assign GPIO_1[15] = 1'b1; // tRIGGER
256 assign GPIO_1[14] = DLY_RST_1;
257
258 assign oLEDR = iSW;
259 assign oLEDG = Y_Cont;
260
261 assign oTD1_RESET_N = 1'b1;
262 assign oVGA_CLOCK = ~VGA_CTRL_CLK;
263
264 assign CCD_MCLK = rClk[0];
265 assign oUART_TXD = iUART_RXD;
266
267 assign adc_penirq_n = GPIO_CLKIN_N0;
268 assign adc_dout = GPIO_0[0];
269 assign adc_busy = GPIO_CLKIN_P0;
270 assign GPIO_0[1] = adc_din;
271 assign GPIO_0[2] = adc_ltm_sclk;
272 assign GPIO_0[3] = ltm_b[3];
273 assign GPIO_0[4] = ltm_b[2];
274 assign GPIO_0[5] = ltm_b[1];
275 assign GPIO_0[6] = ltm_b[0];
276 assign GPIO_0[7] =~ltm_nclk;
277 assign GPIO_0[8] = ltm_den;
278 assign GPIO_0[9] = ltm_hd;
279 assign GPIO_0[10] = ltm_vd;
280 assign GPIO_0[11] = ltm_b[4];
281 assign GPIO_0[12] = ltm_b[5];
282 assign GPIO_0[13] = ltm_b[6];
283 assign GPIO_CLKOUT_N0 = ltm_b[7];
284 assign GPIO_0[14] = ltm_g[0];
285 assign GPIO_CLKOUT_P0 = ltm_g[1];
286 assign GPIO_0[15] = ltm_g[2];
287 assign GPIO_0[16] = ltm_g[3];
288 assign GPIO_0[17] = ltm_g[4];
289 assign GPIO_0[18] = ltm_g[5];
290 assign GPIO_0[19] = ltm_g[6];
291 assign GPIO_0[20] = ltm_g[7];
292 assign GPIO_0[21] = ltm_r[0];
293 assign GPIO_0[22] = ltm_r[1];
294 assign GPIO_0[23] = ltm_r[2];
295 assign GPIO_0[24] = ltm_r[3];
296 assign GPIO_0[25] = ltm_r[4];
297 assign GPIO_0[26] = ltm_r[5];
298 assign GPIO_0[27] = ltm_r[6];
299 assign GPIO_0[28] = ltm_r[7];
300 assign GPIO_0[29] = ltm_grst;
301 assign GPIO_0[30] = ltm_scen;
302 assign GPIO_0[31] = ltm_sda;
303
304 assign ltm_grst = iKEY[0];
305 assign adc_ltm_sclk = ltm_sclk;
306
307 Reset_Delay reset0 (
308 .iCLK(iCLK_50),
309 .iRST(iKEY[0]),
310 .oRST_0(DLY_RST_0),
311 .oRST_1(DLY_RST_1),
312 .oRST_2(DLY_RST_2)
313 );
314
315 CCD_Capture capture0 (
316 .oDATA(mCCD_DATA),
317 .oDVAL(mCCD_DVAL),
318 .oX_Cont(X_Cont),
319 .oY_Cont(Y_Cont),
320 .oFrame_Cont(Frame_Cont),
321 .iDATA(rCCD_DATA),
322 .iFVAL(rCCD_FVAL),
323 .iLVAL(rCCD_LVAL),
324 .iSTART(!iKEY[3]),
325 .iEND(!iKEY[2]),
326 .iCLK(CCD_PIXCLK),
327 .iRST(DLY_RST_2)
328 );
329
330 RAW2RGB rgb0 (
331 .iCLK(CCD_PIXCLK),
332 .iRST_n(DLY_RST_1),
333 .iData(mCCD_DATA),
334 .iDval(mCCD_DVAL),
335 .oRed(sCCD_R),
336 .oGreen(sCCD_G),
337 .oBlue(sCCD_B),
338 .oDval(sCCD_DVAL),
339 .iMIRROR(iSW[17]),
340 .iX_Cont(X_Cont),
341 .iY_Cont(Y_Cont)
342 );
343
344 SEG7_LUT_8 seg0 (
345 .oSEG0(oHEX0_D),
346 .oSEG1(oHEX1_D),
347 .oSEG2(oHEX2_D),
348 .oSEG3(oHEX3_D),
349 .oSEG4(oHEX4_D),
350 .oSEG5(oHEX5_D),
351 .oSEG6(oHEX6_D),
352 .oSEG7(oHEX7_D),
353 .iDIG(Frame_Cont[31:0])
354 );
355
356 vga_pll vga_pll0 (
357 .inclk0(iCLK_50_2),
358 .c0(ltm_nclk)
359 );
360
361 sdram_pll sdram_pll0 (
362 .inclk0(iCLK_50_3),
363 .c0(sdram_ctrl_clk),
364 .c1(oDRAM0_CLK),
365 .c2(oDRAM1_CLK)
366 );
367
368 Sdram_Control_4Port sdram0 (
369 // HOST Side
370 .REF_CLK(iCLK_50),
371 .RESET_N(1'b1),
372 .CLK(sdram_ctrl_clk),
373 // FIFO Write Side 1
374 .WR1_DATA({6'h00, sCCD_G[11:2]}),
375 .WR1(sCCD_DVAL),
376 .WR1_ADDR(0),
377 .WR1_MAX_ADDR(800*480),
378 .WR1_LENGTH(9'h100),
379 .WR1_LOAD(!DLY_RST_0),
380 .WR1_CLK(CCD_PIXCLK),
381 // FIFO Read Side 1
382 .RD1_DATA(Read_DATA1),
383 .RD1(Read),
384 .RD1_ADDR(0),
385 .RD1_MAX_ADDR(800*480),
386 .RD1_LENGTH(9'h100),
387 .RD1_LOAD(!DLY_RST_0),
388 .RD1_CLK(~ltm_nclk),
389 // SDRAM Side
390 .SA(oDRAM0_A[11:0]),
391 .BA(oDRAM0_BA),
392 .CS_N(oDRAM0_CS_N),
393 .CKE(oDRAM0_CKE),
394 .RAS_N(oDRAM0_RAS_N),
395 .CAS_N(oDRAM0_CAS_N),
396 .WE_N(oDRAM0_WE_N),
397 .DQ(DRAM_DQ[15:0]),
398 .DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
399 );
400
401 I2C_CCD_Config ccd_config0 (
402 // Host Side
403 .iCLK(iCLK_50),
404 .iRST_N(DLY_RST_1),
405 .iEXPOSURE_ADJ(iKEY[1]),
406 .iEXPOSURE_DEC_p(iSW[0]),
407 .iMIRROR_SW(iSW[17]),
408 // I2C Side
409 .I2C_SCLK(GPIO_1[20]),
410 .I2C_SDAT(GPIO_1[19])
411 );
412
413 touch_tcon tcon0 (
414 .iCLK(ltm_nclk),
415 .iRST_n(DLY_RST_2),
416 // sdram side
417 .iREAD_DATA1(Read_DATA1),
418 .iREAD_DATA2(Read_DATA2),
419 .oREAD_SDRAM_EN(Read),
420 // lcd side
421 .oLCD_R(ltm_r),
422 .oLCD_G(ltm_g),
423 .oLCD_B(ltm_b),
424 .oHD(ltm_hd),
425 .oVD(ltm_vd),
426 .oDEN(ltm_den)
427 );
428
429 lcd_3wire_config wire0 (
430 // Host Side
431 .iCLK(iCLK_50),
432 .iRST_n(DLY_RST_0),
433 // 3 wire Side
434 .o3WIRE_SCLK(ltm_sclk),
435 .io3WIRE_SDAT(ltm_sda),
436 .o3WIRE_SCEN(ltm_scen),
437 .o3WIRE_BUSY_n(ltm_3wirebusy_n)
438 );
439
440 always@(posedge iCLK_50)
441 rClk <= rClk + 1;
442
443 always@(posedge CCD_PIXCLK) begin
444 rCCD_DATA <= CCD_DATA;
445 rCCD_LVAL <= CCD_LVAL;
446 rCCD_FVAL <= CCD_FVAL;
447 end
448
449 endmodule
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : DE2_70.v
5 Compiler : Quartus II 7.2 SP3
6 Description : Demo how to use TRDB-D5M with LTM to make gray before SDRAM on DE2-70
7 Release : 08/23/2008 1.0
8 */
9
10 module DE2_70 (
11 //////////////////////// Clock Input ////////////////////////
12 input iCLK_28, // 28.63636 MHz
13 input iCLK_50, // 50 MHz
14 input iCLK_50_2, // 50 MHz
15 input iCLK_50_3, // 50 MHz
16 input iCLK_50_4, // 50 MHz
17 input iEXT_CLOCK, // External Clock
18 //////////////////////// Push Button ////////////////////////
19 input [3:0] iKEY, // Pushbutton[3:0]
20 //////////////////////// DPDT Switch ////////////////////////
21 input [17:0] iSW, // Toggle Switch[17:0]
22 //////////////////////// 7-SEG Dispaly ////////////////////////
23 output [6:0] oHEX0_D, // Seven Segment Digit 0
24 output oHEX0_DP, // Seven Segment Digit 0 decimal point
25 output [6:0] oHEX1_D, // Seven Segment Digit 1
26 output oHEX1_DP, // Seven Segment Digit 1 decimal point
27 output [6:0] oHEX2_D, // Seven Segment Digit 2
28 output oHEX2_DP, // Seven Segment Digit 2 decimal point
29 output [6:0] oHEX3_D, // Seven Segment Digit 3
30 output oHEX3_DP, // Seven Segment Digit 3 decimal point
31 output [6:0] oHEX4_D, // Seven Segment Digit 4
32 output oHEX4_DP, // Seven Segment Digit 4 decimal point
33 output [6:0] oHEX5_D, // Seven Segment Digit 5
34 output oHEX5_DP, // Seven Segment Digit 5 decimal point
35 output [6:0] oHEX6_D, // Seven Segment Digit 6
36 output oHEX6_DP, // Seven Segment Digit 6 decimal point
37 output [6:0] oHEX7_D, // Seven Segment Digit 7
38 output oHEX7_DP, // Seven Segment Digit 7 decimal point
39 //////////////////////////// LED ////////////////////////////
40 output [8:0] oLEDG, // LED Green[8:0]
41 output [17:0] oLEDR, // LED Red[17:0]
42 //////////////////////////// UART ////////////////////////////
43 output oUART_TXD, // UART Transmitter
44 input iUART_RXD, // UART Receiver
45 output oUART_CTS, // UART Clear To Send
46 input iUART_RTS, // UART Requst To Send
47 //////////////////////////// IRDA ////////////////////////////
48 output oIRDA_TXD, // IRDA Transmitter
49 input iIRDA_RXD, // IRDA Receiver
50 /////////////////////// SDRAM Interface ////////////////////////
51 inout [31:0] DRAM_DQ, // SDRAM Data bus 32 Bits
52 output [12:0] oDRAM0_A, // SDRAM0 Address bus 13 Bits
53 output [12:0] oDRAM1_A, // SDRAM1 Address bus 13 Bits
54 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
55 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
56 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
57 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
58 output oDRAM0_WE_N, // SDRAM0 Write Enable
59 output oDRAM1_WE_N, // SDRAM1 Write Enable
60 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
61 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
62 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
63 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
64 output oDRAM0_CS_N, // SDRAM0 Chip Select
65 output oDRAM1_CS_N, // SDRAM1 Chip Select
66 output [1:0] oDRAM0_BA, // SDRAM0 Bank Address
67 output [1:0] oDRAM1_BA, // SDRAM1 Bank Address
68 output oDRAM0_CLK, // SDRAM0 Clock
69 output oDRAM1_CLK, // SDRAM1 Clock
70 output oDRAM0_CKE, // SDRAM0 Clock Enable
71 output oDRAM1_CKE, // SDRAM1 Clock Enable
72 //////////////////////// Flash Interface ////////////////////////
73 inout [14:0] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
74 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
75 output [21:0] oFLASH_A, // FLASH Address bus 26 Bits
76 output oFLASH_WE_N, // FLASH Write Enable
77 output oFLASH_RST_N, // FLASH Reset
78 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
79 input iFLASH_RY_N, // FLASH Ready/Busy output
80 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
81 output oFLASH_OE_N, // FLASH Output Enable
82 output oFLASH_CE_N, // FLASH Chip Enable
83 //////////////////////// SRAM Interface ////////////////////////
84 inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
85 inout [3:0] SRAM_DPA, // SRAM Parity Data Bus
86 output [18:0] oSRAM_A, // SRAM Address bus 21 Bits
87 output oSRAM_ADSC_N, // SRAM Controller Address Status
88 output oSRAM_ADSP_N, // SRAM Processor Address Status
89 output oSRAM_ADV_N, // SRAM Burst Address Advance
90 output [3:0] oSRAM_BE_N, // SRAM Byte Write Enable
91 output oSRAM_CE1_N, // SRAM Chip Enable
92 output oSRAM_CE2, // SRAM Chip Enable
93 output oSRAM_CE3_N, // SRAM Chip Enable
94 output oSRAM_CLK, // SRAM Clock
95 output oSRAM_GW_N, // SRAM Global Write Enable
96 output oSRAM_OE_N, // SRAM Output Enable
97 output oSRAM_WE_N, // SRAM Write Enable
98 //////////////////// ISP1362 Interface ////////////////////////
99 inout [15:0] OTG_D, // ISP1362 Data bus 16 Bits
100 output [1:0] oOTG_A, // ISP1362 Address 2 Bits
101 output oOTG_CS_N, // ISP1362 Chip Select
102 output oOTG_OE_N, // ISP1362 Read
103 output oOTG_WE_N, // ISP1362 Write
104 output oOTG_RESET_N, // ISP1362 Reset
105 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
106 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
107 input iOTG_INT0, // ISP1362 Interrupt 0
108 input iOTG_INT1, // ISP1362 Interrupt 1
109 input iOTG_DREQ0, // ISP1362 DMA Request 0
110 input iOTG_DREQ1, // ISP1362 DMA Request 1
111 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
112 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
113 //////////////////// LCD Module 16X2 ////////////////////////////
114 inout [7:0] LCD_D, // LCD Data bus 8 bits
115 output oLCD_ON, // LCD Power ON/OFF
116 output oLCD_BLON, // LCD Back Light ON/OFF
117 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
118 output oLCD_EN, // LCD Enable
119 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
120 //////////////////// SD Card Interface ////////////////////////
121 inout SD_DAT, // SD Card Data
122 inout SD_DAT3, // SD Card Data 3
123 inout SD_CMD, // SD Card Command Signal
124 output oSD_CLK, // SD Card Clock
125 //////////////////////// I2C ////////////////////////////////
126 inout I2C_SDAT, // I2C Data
127 output oI2C_SCLK, // I2C Clock
128 //////////////////////// PS2 ////////////////////////////////
129 inout PS2_KBDAT, // PS2 Keyboard Data
130 inout PS2_KBCLK, // PS2 Keyboard Clock
131 inout PS2_MSDAT, // PS2 Mouse Data
132 inout PS2_MSCLK, // PS2 Mouse Clock
133 //////////////////////// VGA ////////////////////////////
134 output oVGA_CLOCK, // VGA Clock
135 output oVGA_HS, // VGA H_SYNC
136 output oVGA_VS, // VGA V_SYNC
137 output oVGA_BLANK_N, // VGA BLANK
138 output oVGA_SYNC_N, // VGA SYNC
139 output [9:0] oVGA_R, // VGA Red[9:0]
140 output [9:0] oVGA_G, // VGA Green[9:0]
141 output [9:0] oVGA_B, // VGA Blue[9:0]
142 //////////////// Ethernet Interface ////////////////////////////
143 inout [15:0] ENET_D, // DM9000A DATA bus 16Bits
144 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
145 output oENET_CS_N, // DM9000A Chip Select
146 output oENET_IOW_N, // DM9000A Write
147 output oENET_IOR_N, // DM9000A Read
148 output oENET_RESET_N, // DM9000A Reset
149 input iENET_INT, // DM9000A Interrupt
150 output oENET_CLK, // DM9000A Clock 25 MHz
151 //////////////////// Audio CODEC ////////////////////////////
152 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
153 input iAUD_ADCDAT, // Audio CODEC ADC Data
154 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
155 output oAUD_DACDAT, // Audio CODEC DAC Data
156 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
157 output oAUD_XCK, // Audio CODEC Chip Clock
158 //////////////////// TV Devoder ////////////////////////////
159 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
160 input [7:0] iTD1_D, // TV Decoder1 Data bus 8 bits
161 input iTD1_HS, // TV Decoder1 H_SYNC
162 input iTD1_VS, // TV Decoder1 V_SYNC
163 output oTD1_RESET_N, // TV Decoder1 Reset
164 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
165 input [7:0] iTD2_D, // TV Decoder2 Data bus 8 bits
166 input iTD2_HS, // TV Decoder2 H_SYNC
167 input iTD2_VS, // TV Decoder2 V_SYNC
168 output oTD2_RESET_N, // TV Decoder2 Reset
169 //////////////////////// GPIO ////////////////////////////////
170 inout [31:0] GPIO_0, // GPIO Connection 0 I/O
171 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
172 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
173 inout GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
174 inout GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
175 inout [31:0] GPIO_1, // GPIO Connection 1 I/O
176 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
177 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
178 inout GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
179 inout GPIO_CLKOUT_P1 // GPIO Connection 1 Clock Output 1
180 );
181
182 // CCD
183 wire [11:0] CCD_DATA;
184 wire CCD_SDAT;
185 wire CCD_SCLK;
186 wire CCD_FLASH;
187 wire CCD_FVAL;
188 wire CCD_LVAL;
189 wire CCD_PIXCLK;
190 wire CCD_MCLK; // CCD Master Clock
191
192 wire [15:0] Read_DATA1;
193 wire [15:0] Read_DATA2;
194 wire VGA_CTRL_CLK;
195 wire [11:0] mCCD_DATA;
196 wire mCCD_DVAL;
197 wire mCCD_DVAL_d;
198 wire [15:0] X_Cont;
199 wire [15:0] Y_Cont;
200 wire [9:0] X_ADDR;
201 wire [31:0] Frame_Cont;
202 wire DLY_RST_0;
203 wire DLY_RST_1;
204 wire DLY_RST_2;
205 wire Read;
206 reg [11:0] rCCD_DATA;
207 reg rCCD_LVAL;
208 reg rCCD_FVAL;
209 wire [11:0] sCCD_R;
210 wire [11:0] sCCD_G;
211 wire [11:0] sCCD_B;
212 wire sCCD_DVAL;
213 reg [1:0] rClk;
214 wire sdram_ctrl_clk;
215
216 // Touch panel signal
217 wire [7:0] ltm_r; // LTM Red Data 8 Bits
218 wire [7:0] ltm_g; // LTM Green Data 8 Bits
219 wire [7:0] ltm_b; // LTM Blue Data 8 Bits
220 wire ltm_nclk; // LTM Clcok
221 wire ltm_hd;
222 wire ltm_vd;
223 wire ltm_den;
224 wire adc_dclk;
225 wire adc_cs;
226 wire adc_penirq_n;
227 wire adc_busy;
228 wire adc_din;
229 wire adc_dout;
230 wire adc_ltm_sclk;
231 wire ltm_grst;
232
233 // LTM Config
234 wire ltm_sclk;
235 wire ltm_sda;
236 wire ltm_scen;
237 wire ltm_3wirebusy_n;
238
239 assign CCD_DATA[0] = GPIO_1[11];
240 assign CCD_DATA[1] = GPIO_1[10];
241 assign CCD_DATA[2] = GPIO_1[9];
242 assign CCD_DATA[3] = GPIO_1[8];
243 assign CCD_DATA[4] = GPIO_1[7];
244 assign CCD_DATA[5] = GPIO_1[6];
245 assign CCD_DATA[6] = GPIO_1[5];
246 assign CCD_DATA[7] = GPIO_1[4];
247 assign CCD_DATA[8] = GPIO_1[3];
248 assign CCD_DATA[9] = GPIO_1[2];
249 assign CCD_DATA[10] = GPIO_1[1];
250 assign CCD_DATA[11] = GPIO_1[0];
251 assign GPIO_CLKOUT_N1 = CCD_MCLK;
252 assign CCD_FVAL = GPIO_1[18];
253 assign CCD_LVAL = GPIO_1[17];
254 assign CCD_PIXCLK = GPIO_CLKIN_N1;
255 assign GPIO_1[15] = 1'b1; // tRIGGER
256 assign GPIO_1[14] = DLY_RST_1;
257
258 assign oLEDR = iSW;
259 assign oLEDG = Y_Cont;
260
261 assign oTD1_RESET_N = 1'b1;
262 assign oVGA_CLOCK = ~VGA_CTRL_CLK;
263
264 assign CCD_MCLK = rClk[0];
265 assign oUART_TXD = iUART_RXD;
266
267 assign adc_penirq_n = GPIO_CLKIN_N0;
268 assign adc_dout = GPIO_0[0];
269 assign adc_busy = GPIO_CLKIN_P0;
270 assign GPIO_0[1] = adc_din;
271 assign GPIO_0[2] = adc_ltm_sclk;
272 assign GPIO_0[3] = ltm_b[3];
273 assign GPIO_0[4] = ltm_b[2];
274 assign GPIO_0[5] = ltm_b[1];
275 assign GPIO_0[6] = ltm_b[0];
276 assign GPIO_0[7] =~ltm_nclk;
277 assign GPIO_0[8] = ltm_den;
278 assign GPIO_0[9] = ltm_hd;
279 assign GPIO_0[10] = ltm_vd;
280 assign GPIO_0[11] = ltm_b[4];
281 assign GPIO_0[12] = ltm_b[5];
282 assign GPIO_0[13] = ltm_b[6];
283 assign GPIO_CLKOUT_N0 = ltm_b[7];
284 assign GPIO_0[14] = ltm_g[0];
285 assign GPIO_CLKOUT_P0 = ltm_g[1];
286 assign GPIO_0[15] = ltm_g[2];
287 assign GPIO_0[16] = ltm_g[3];
288 assign GPIO_0[17] = ltm_g[4];
289 assign GPIO_0[18] = ltm_g[5];
290 assign GPIO_0[19] = ltm_g[6];
291 assign GPIO_0[20] = ltm_g[7];
292 assign GPIO_0[21] = ltm_r[0];
293 assign GPIO_0[22] = ltm_r[1];
294 assign GPIO_0[23] = ltm_r[2];
295 assign GPIO_0[24] = ltm_r[3];
296 assign GPIO_0[25] = ltm_r[4];
297 assign GPIO_0[26] = ltm_r[5];
298 assign GPIO_0[27] = ltm_r[6];
299 assign GPIO_0[28] = ltm_r[7];
300 assign GPIO_0[29] = ltm_grst;
301 assign GPIO_0[30] = ltm_scen;
302 assign GPIO_0[31] = ltm_sda;
303
304 assign ltm_grst = iKEY[0];
305 assign adc_ltm_sclk = ltm_sclk;
306
307 Reset_Delay reset0 (
308 .iCLK(iCLK_50),
309 .iRST(iKEY[0]),
310 .oRST_0(DLY_RST_0),
311 .oRST_1(DLY_RST_1),
312 .oRST_2(DLY_RST_2)
313 );
314
315 CCD_Capture capture0 (
316 .oDATA(mCCD_DATA),
317 .oDVAL(mCCD_DVAL),
318 .oX_Cont(X_Cont),
319 .oY_Cont(Y_Cont),
320 .oFrame_Cont(Frame_Cont),
321 .iDATA(rCCD_DATA),
322 .iFVAL(rCCD_FVAL),
323 .iLVAL(rCCD_LVAL),
324 .iSTART(!iKEY[3]),
325 .iEND(!iKEY[2]),
326 .iCLK(CCD_PIXCLK),
327 .iRST(DLY_RST_2)
328 );
329
330 RAW2RGB rgb0 (
331 .iCLK(CCD_PIXCLK),
332 .iRST_n(DLY_RST_1),
333 .iData(mCCD_DATA),
334 .iDval(mCCD_DVAL),
335 .oRed(sCCD_R),
336 .oGreen(sCCD_G),
337 .oBlue(sCCD_B),
338 .oDval(sCCD_DVAL),
339 .iMIRROR(iSW[17]),
340 .iX_Cont(X_Cont),
341 .iY_Cont(Y_Cont)
342 );
343
344 SEG7_LUT_8 seg0 (
345 .oSEG0(oHEX0_D),
346 .oSEG1(oHEX1_D),
347 .oSEG2(oHEX2_D),
348 .oSEG3(oHEX3_D),
349 .oSEG4(oHEX4_D),
350 .oSEG5(oHEX5_D),
351 .oSEG6(oHEX6_D),
352 .oSEG7(oHEX7_D),
353 .iDIG(Frame_Cont[31:0])
354 );
355
356 vga_pll vga_pll0 (
357 .inclk0(iCLK_50_2),
358 .c0(ltm_nclk)
359 );
360
361 sdram_pll sdram_pll0 (
362 .inclk0(iCLK_50_3),
363 .c0(sdram_ctrl_clk),
364 .c1(oDRAM0_CLK),
365 .c2(oDRAM1_CLK)
366 );
367
368 Sdram_Control_4Port sdram0 (
369 // HOST Side
370 .REF_CLK(iCLK_50),
371 .RESET_N(1'b1),
372 .CLK(sdram_ctrl_clk),
373 // FIFO Write Side 1
374 .WR1_DATA({6'h00, sCCD_G[11:2]}),
375 .WR1(sCCD_DVAL),
376 .WR1_ADDR(0),
377 .WR1_MAX_ADDR(800*480),
378 .WR1_LENGTH(9'h100),
379 .WR1_LOAD(!DLY_RST_0),
380 .WR1_CLK(CCD_PIXCLK),
381 // FIFO Read Side 1
382 .RD1_DATA(Read_DATA1),
383 .RD1(Read),
384 .RD1_ADDR(0),
385 .RD1_MAX_ADDR(800*480),
386 .RD1_LENGTH(9'h100),
387 .RD1_LOAD(!DLY_RST_0),
388 .RD1_CLK(~ltm_nclk),
389 // SDRAM Side
390 .SA(oDRAM0_A[11:0]),
391 .BA(oDRAM0_BA),
392 .CS_N(oDRAM0_CS_N),
393 .CKE(oDRAM0_CKE),
394 .RAS_N(oDRAM0_RAS_N),
395 .CAS_N(oDRAM0_CAS_N),
396 .WE_N(oDRAM0_WE_N),
397 .DQ(DRAM_DQ[15:0]),
398 .DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
399 );
400
401 I2C_CCD_Config ccd_config0 (
402 // Host Side
403 .iCLK(iCLK_50),
404 .iRST_N(DLY_RST_1),
405 .iEXPOSURE_ADJ(iKEY[1]),
406 .iEXPOSURE_DEC_p(iSW[0]),
407 .iMIRROR_SW(iSW[17]),
408 // I2C Side
409 .I2C_SCLK(GPIO_1[20]),
410 .I2C_SDAT(GPIO_1[19])
411 );
412
413 touch_tcon tcon0 (
414 .iCLK(ltm_nclk),
415 .iRST_n(DLY_RST_2),
416 // sdram side
417 .iREAD_DATA1(Read_DATA1),
418 .iREAD_DATA2(Read_DATA2),
419 .oREAD_SDRAM_EN(Read),
420 // lcd side
421 .oLCD_R(ltm_r),
422 .oLCD_G(ltm_g),
423 .oLCD_B(ltm_b),
424 .oHD(ltm_hd),
425 .oVD(ltm_vd),
426 .oDEN(ltm_den)
427 );
428
429 lcd_3wire_config wire0 (
430 // Host Side
431 .iCLK(iCLK_50),
432 .iRST_n(DLY_RST_0),
433 // 3 wire Side
434 .o3WIRE_SCLK(ltm_sclk),
435 .io3WIRE_SDAT(ltm_sda),
436 .o3WIRE_SCEN(ltm_scen),
437 .o3WIRE_BUSY_n(ltm_3wirebusy_n)
438 );
439
440 always@(posedge iCLK_50)
441 rClk <= rClk + 1;
442
443 always@(posedge CCD_PIXCLK) begin
444 rCCD_DATA <= CCD_DATA;
445 rCCD_LVAL <= CCD_LVAL;
446 rCCD_FVAL <= CCD_FVAL;
447 end
448
449 endmodule
368行
Sdram_Control_4Port sdram0 (
// HOST Side
.REF_CLK(iCLK_50),
.RESET_N(1'b1),
.CLK(sdram_ctrl_clk),
// FIFO Write Side 1
.WR1_DATA({6'h00, sCCD_G[11:2]}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(800*480),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD_PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(Read),
.RD1_ADDR(0),
.RD1_MAX_ADDR(800*480),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(~ltm_nclk),
// SDRAM Side
.SA(oDRAM0_A[11:0]),
.BA(oDRAM0_BA),
.CS_N(oDRAM0_CS_N),
.CKE(oDRAM0_CKE),
.RAS_N(oDRAM0_RAS_N),
.CAS_N(oDRAM0_CAS_N),
.WE_N(oDRAM0_WE_N),
.DQ(DRAM_DQ[15:0]),
.DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
);
// HOST Side
.REF_CLK(iCLK_50),
.RESET_N(1'b1),
.CLK(sdram_ctrl_clk),
// FIFO Write Side 1
.WR1_DATA({6'h00, sCCD_G[11:2]}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(800*480),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD_PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(Read),
.RD1_ADDR(0),
.RD1_MAX_ADDR(800*480),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(~ltm_nclk),
// SDRAM Side
.SA(oDRAM0_A[11:0]),
.BA(oDRAM0_BA),
.CS_N(oDRAM0_CS_N),
.CKE(oDRAM0_CKE),
.RAS_N(oDRAM0_RAS_N),
.CAS_N(oDRAM0_CAS_N),
.WE_N(oDRAM0_WE_N),
.DQ(DRAM_DQ[15:0]),
.DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
);
在(原創) 如何Real Time產生灰階影像? (SOC) (DE2) (TRDB-DC2)曾提過，寫在SDRAM之前的優點是節省SDRAM空間，節省頻寬，由於DE2-70有兩顆32MB SDRAM，在空間上不是問題，在DE2_70_D5M_LTM範例中，已經將G、B放在第1顆SDRAM，G、R放在第2顆SDRAM，這樣的優點是SDRAM頻寬可以加倍。由於灰階只需要G，在DE2-70只要1顆SDRAM即可，另外一顆SDRAM完全不須使用，一樣可以省下一半的SDRAM空間，不過因為一樣是1 read 1 write，所以並沒有省下頻寬。
touch_tcon.v / Verilog
1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : touch_tcon.v
5 Compiler : Quartus II 7.2 SP3
6 Description : Demo how to use TRDB-D5M with LTM to make gray before SDRAM on DE2-70
7 Release : 08/23/2008 1.0
8 */
9
10 module touch_tcon (
11 input iCLK, // LCD display clock
12 input iRST_n, // systen reset
13 // SDRAM SIDE
14 input [15:0] iREAD_DATA1, // R and G color data form sdram
15 input [15:0] iREAD_DATA2, // B color data form sdram
16 output oREAD_SDRAM_EN, // read sdram data control signal
17 //LCD SIDE
18 output reg oHD, // LCD Horizontal sync
19 output reg oVD, // LCD Vertical sync
20 output reg oDEN, // LCD Data Enable
21 output reg [7:0] oLCD_R, // LCD Red color data
22 output reg [7:0] oLCD_G, // LCD Green color data
23 output reg [7:0] oLCD_B // LCD Blue color data
24 );
25
26 parameter H_LINE = 1056;
27 parameter V_LINE = 525;
28 parameter Hsync_Blank = 216;
29 parameter Hsync_Front_Porch = 40;
30 parameter Vertical_Back_Porch = 35;
31 parameter Vertical_Front_Porch = 10;
32
33 reg [10:0] x_cnt;
34 reg [9:0] y_cnt;
35 wire [7:0] read_red;
36 wire [7:0] read_green;
37 wire [7:0] read_blue;
38 wire display_area;
39 reg mhd;
40 reg mvd;
41 reg mden;
42
43 // This signal control reading data form SDRAM , if high read color data form sdram .
44 assign oREAD_SDRAM_EN = ( (x_cnt>Hsync_Blank-2)&&
45 (x_cnt<(H_LINE-Hsync_Front_Porch-1))&&
46 (y_cnt>(Vertical_Back_Porch-1))&&
47 (y_cnt<(V_LINE - Vertical_Front_Porch))
48 )? 1'b1 : 1'b0;
49
50 // This signal indicate the lcd display area .
51 assign display_area = ((x_cnt>(Hsync_Blank-1)&& //>215
52 (x_cnt<(H_LINE-Hsync_Front_Porch))&& //< 1016
53 (y_cnt>(Vertical_Back_Porch-1))&&
54 (y_cnt<(V_LINE - Vertical_Front_Porch))
55 )) ? 1'b1 : 1'b0;
56
57 assign read_red = display_area ? iREAD_DATA1[9:2] : 8'b0;
58 assign read_green = display_area ? iREAD_DATA1[9:2] : 8'b0;
59 assign read_blue = display_area ? iREAD_DATA1[9:2] : 8'b0;
60
61 ///////////////////////// x y counter and lcd hd generator //////////////////
62 always@(posedge iCLK or negedge iRST_n) begin
63 if (!iRST_n) begin
64 x_cnt <= 11'd0;
65 mhd <= 1'd0;
66 end
67 else if (x_cnt == (H_LINE-1)) begin
68 x_cnt <= 11'd0;
69 mhd <= 1'd0;
70 end
71 else begin
72 x_cnt <= x_cnt + 11'd1;
73 mhd <= 1'd1;
74 end
75 end
76
77 always@(posedge iCLK or negedge iRST_n) begin
78 if (!iRST_n)
79 y_cnt <= 10'd0;
80 else if (x_cnt == (H_LINE-1)) begin
81 if (y_cnt == (V_LINE-1))
82 y_cnt <= 10'd0;
83 else
84 y_cnt <= y_cnt + 10'd1;
85 end
86 end
87
88 ////////////////////////////// touch panel timing //////////////////
89 always@(posedge iCLK or negedge iRST_n) begin
90 if (!iRST_n)
91 mvd <= 1'b1;
92 else if (y_cnt == 10'd0)
93 mvd <= 1'b0;
94 else
95 mvd <= 1'b1;
96 end
97
98 always@(posedge iCLK or negedge iRST_n) begin
99 if (!iRST_n)
100 mden <= 1'b0;
101 else if (display_area)
102 mden <= 1'b1;
103 else
104 mden <= 1'b0;
105 end
106
107 always@(posedge iCLK or negedge iRST_n) begin
108 if (!iRST_n) begin
109 oHD <= 1'd0;
110 oVD <= 1'd0;
111 oDEN <= 1'd0;
112 oLCD_R <= 8'd0;
113 oLCD_G <= 8'd0;
114 oLCD_B <= 8'd0;
115 end
116 else begin
117 oHD <= mhd;
118 oVD <= mvd;
119 oDEN <= mden;
120 oLCD_R <= read_red;
121 oLCD_G <= read_green;
122 oLCD_B <= read_blue;
123 end
124 end
125
126 endmodule
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : touch_tcon.v
5 Compiler : Quartus II 7.2 SP3
6 Description : Demo how to use TRDB-D5M with LTM to make gray before SDRAM on DE2-70
7 Release : 08/23/2008 1.0
8 */
9
10 module touch_tcon (
11 input iCLK, // LCD display clock
12 input iRST_n, // systen reset
13 // SDRAM SIDE
14 input [15:0] iREAD_DATA1, // R and G color data form sdram
15 input [15:0] iREAD_DATA2, // B color data form sdram
16 output oREAD_SDRAM_EN, // read sdram data control signal
17 //LCD SIDE
18 output reg oHD, // LCD Horizontal sync
19 output reg oVD, // LCD Vertical sync
20 output reg oDEN, // LCD Data Enable
21 output reg [7:0] oLCD_R, // LCD Red color data
22 output reg [7:0] oLCD_G, // LCD Green color data
23 output reg [7:0] oLCD_B // LCD Blue color data
24 );
25
26 parameter H_LINE = 1056;
27 parameter V_LINE = 525;
28 parameter Hsync_Blank = 216;
29 parameter Hsync_Front_Porch = 40;
30 parameter Vertical_Back_Porch = 35;
31 parameter Vertical_Front_Porch = 10;
32
33 reg [10:0] x_cnt;
34 reg [9:0] y_cnt;
35 wire [7:0] read_red;
36 wire [7:0] read_green;
37 wire [7:0] read_blue;
38 wire display_area;
39 reg mhd;
40 reg mvd;
41 reg mden;
42
43 // This signal control reading data form SDRAM , if high read color data form sdram .
44 assign oREAD_SDRAM_EN = ( (x_cnt>Hsync_Blank-2)&&
45 (x_cnt<(H_LINE-Hsync_Front_Porch-1))&&
46 (y_cnt>(Vertical_Back_Porch-1))&&
47 (y_cnt<(V_LINE - Vertical_Front_Porch))
48 )? 1'b1 : 1'b0;
49
50 // This signal indicate the lcd display area .
51 assign display_area = ((x_cnt>(Hsync_Blank-1)&& //>215
52 (x_cnt<(H_LINE-Hsync_Front_Porch))&& //< 1016
53 (y_cnt>(Vertical_Back_Porch-1))&&
54 (y_cnt<(V_LINE - Vertical_Front_Porch))
55 )) ? 1'b1 : 1'b0;
56
57 assign read_red = display_area ? iREAD_DATA1[9:2] : 8'b0;
58 assign read_green = display_area ? iREAD_DATA1[9:2] : 8'b0;
59 assign read_blue = display_area ? iREAD_DATA1[9:2] : 8'b0;
60
61 ///////////////////////// x y counter and lcd hd generator //////////////////
62 always@(posedge iCLK or negedge iRST_n) begin
63 if (!iRST_n) begin
64 x_cnt <= 11'd0;
65 mhd <= 1'd0;
66 end
67 else if (x_cnt == (H_LINE-1)) begin
68 x_cnt <= 11'd0;
69 mhd <= 1'd0;
70 end
71 else begin
72 x_cnt <= x_cnt + 11'd1;
73 mhd <= 1'd1;
74 end
75 end
76
77 always@(posedge iCLK or negedge iRST_n) begin
78 if (!iRST_n)
79 y_cnt <= 10'd0;
80 else if (x_cnt == (H_LINE-1)) begin
81 if (y_cnt == (V_LINE-1))
82 y_cnt <= 10'd0;
83 else
84 y_cnt <= y_cnt + 10'd1;
85 end
86 end
87
88 ////////////////////////////// touch panel timing //////////////////
89 always@(posedge iCLK or negedge iRST_n) begin
90 if (!iRST_n)
91 mvd <= 1'b1;
92 else if (y_cnt == 10'd0)
93 mvd <= 1'b0;
94 else
95 mvd <= 1'b1;
96 end
97
98 always@(posedge iCLK or negedge iRST_n) begin
99 if (!iRST_n)
100 mden <= 1'b0;
101 else if (display_area)
102 mden <= 1'b1;
103 else
104 mden <= 1'b0;
105 end
106
107 always@(posedge iCLK or negedge iRST_n) begin
108 if (!iRST_n) begin
109 oHD <= 1'd0;
110 oVD <= 1'd0;
111 oDEN <= 1'd0;
112 oLCD_R <= 8'd0;
113 oLCD_G <= 8'd0;
114 oLCD_B <= 8'd0;
115 end
116 else begin
117 oHD <= mhd;
118 oVD <= mvd;
119 oDEN <= mden;
120 oLCD_R <= read_red;
121 oLCD_G <= read_green;
122 oLCD_B <= read_blue;
123 end
124 end
125
126 endmodule
不同於DE2，在DE2-70連touch_tcon.v也要小改，touch_tcon.v相當於DE2_CCD的VGA_Controller.v的地位。
57行
assign read_red = display_area ? iREAD_DATA1[9:2] : 8'b0;
assign read_green = display_area ? iREAD_DATA1[9:2] : 8'b0;
assign read_blue = display_area ? iREAD_DATA1[9:2] : 8'b0;
assign read_green = display_area ? iREAD_DATA1[9:2] : 8'b0;
assign read_blue = display_area ? iREAD_DATA1[9:2] : 8'b0;
由於現在SDRAM只有G，也就是只有iREAD_DATA1，所以R、G、B的輸出完全用G取代。
Method 2：
在SDRAM之後
DE2_70.v / Verilog
1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : DE2_70.v
5 Compiler : Quartus II 7.2 SP3
6 Description : Demo how to use TRDB-D5M with LTM to make gray on DE2-70 after SDRAM
7 Release : 08/23/2008 1.0
8 */
9
10 module DE2_70 (
11 //////////////////////// Clock Input ////////////////////////
12 input iCLK_28, // 28.63636 MHz
13 input iCLK_50, // 50 MHz
14 input iCLK_50_2, // 50 MHz
15 input iCLK_50_3, // 50 MHz
16 input iCLK_50_4, // 50 MHz
17 input iEXT_CLOCK, // External Clock
18 //////////////////////// Push Button ////////////////////////
19 input [3:0] iKEY, // Pushbutton[3:0]
20 //////////////////////// DPDT Switch ////////////////////////
21 input [17:0] iSW, // Toggle Switch[17:0]
22 //////////////////////// 7-SEG Dispaly ////////////////////////
23 output [6:0] oHEX0_D, // Seven Segment Digit 0
24 output oHEX0_DP, // Seven Segment Digit 0 decimal point
25 output [6:0] oHEX1_D, // Seven Segment Digit 1
26 output oHEX1_DP, // Seven Segment Digit 1 decimal point
27 output [6:0] oHEX2_D, // Seven Segment Digit 2
28 output oHEX2_DP, // Seven Segment Digit 2 decimal point
29 output [6:0] oHEX3_D, // Seven Segment Digit 3
30 output oHEX3_DP, // Seven Segment Digit 3 decimal point
31 output [6:0] oHEX4_D, // Seven Segment Digit 4
32 output oHEX4_DP, // Seven Segment Digit 4 decimal point
33 output [6:0] oHEX5_D, // Seven Segment Digit 5
34 output oHEX5_DP, // Seven Segment Digit 5 decimal point
35 output [6:0] oHEX6_D, // Seven Segment Digit 6
36 output oHEX6_DP, // Seven Segment Digit 6 decimal point
37 output [6:0] oHEX7_D, // Seven Segment Digit 7
38 output oHEX7_DP, // Seven Segment Digit 7 decimal point
39 //////////////////////////// LED ////////////////////////////
40 output [8:0] oLEDG, // LED Green[8:0]
41 output [17:0] oLEDR, // LED Red[17:0]
42 //////////////////////////// UART ////////////////////////////
43 output oUART_TXD, // UART Transmitter
44 input iUART_RXD, // UART Receiver
45 output oUART_CTS, // UART Clear To Send
46 input iUART_RTS, // UART Requst To Send
47 //////////////////////////// IRDA ////////////////////////////
48 output oIRDA_TXD, // IRDA Transmitter
49 input iIRDA_RXD, // IRDA Receiver
50 /////////////////////// SDRAM Interface ////////////////////////
51 inout [31:0] DRAM_DQ, // SDRAM Data bus 32 Bits
52 output [12:0] oDRAM0_A, // SDRAM0 Address bus 13 Bits
53 output [12:0] oDRAM1_A, // SDRAM1 Address bus 13 Bits
54 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
55 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
56 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
57 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
58 output oDRAM0_WE_N, // SDRAM0 Write Enable
59 output oDRAM1_WE_N, // SDRAM1 Write Enable
60 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
61 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
62 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
63 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
64 output oDRAM0_CS_N, // SDRAM0 Chip Select
65 output oDRAM1_CS_N, // SDRAM1 Chip Select
66 output [1:0] oDRAM0_BA, // SDRAM0 Bank Address
67 output [1:0] oDRAM1_BA, // SDRAM1 Bank Address
68 output oDRAM0_CLK, // SDRAM0 Clock
69 output oDRAM1_CLK, // SDRAM1 Clock
70 output oDRAM0_CKE, // SDRAM0 Clock Enable
71 output oDRAM1_CKE, // SDRAM1 Clock Enable
72 //////////////////////// Flash Interface ////////////////////////
73 inout [14:0] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
74 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
75 output [21:0] oFLASH_A, // FLASH Address bus 26 Bits
76 output oFLASH_WE_N, // FLASH Write Enable
77 output oFLASH_RST_N, // FLASH Reset
78 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
79 input iFLASH_RY_N, // FLASH Ready/Busy output
80 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
81 output oFLASH_OE_N, // FLASH Output Enable
82 output oFLASH_CE_N, // FLASH Chip Enable
83 //////////////////////// SRAM Interface ////////////////////////
84 inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
85 inout [3:0] SRAM_DPA, // SRAM Parity Data Bus
86 output [18:0] oSRAM_A, // SRAM Address bus 21 Bits
87 output oSRAM_ADSC_N, // SRAM Controller Address Status
88 output oSRAM_ADSP_N, // SRAM Processor Address Status
89 output oSRAM_ADV_N, // SRAM Burst Address Advance
90 output [3:0] oSRAM_BE_N, // SRAM Byte Write Enable
91 output oSRAM_CE1_N, // SRAM Chip Enable
92 output oSRAM_CE2, // SRAM Chip Enable
93 output oSRAM_CE3_N, // SRAM Chip Enable
94 output oSRAM_CLK, // SRAM Clock
95 output oSRAM_GW_N, // SRAM Global Write Enable
96 output oSRAM_OE_N, // SRAM Output Enable
97 output oSRAM_WE_N, // SRAM Write Enable
98 //////////////////// ISP1362 Interface ////////////////////////
99 inout [15:0] OTG_D, // ISP1362 Data bus 16 Bits
100 output [1:0] oOTG_A, // ISP1362 Address 2 Bits
101 output oOTG_CS_N, // ISP1362 Chip Select
102 output oOTG_OE_N, // ISP1362 Read
103 output oOTG_WE_N, // ISP1362 Write
104 output oOTG_RESET_N, // ISP1362 Reset
105 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
106 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
107 input iOTG_INT0, // ISP1362 Interrupt 0
108 input iOTG_INT1, // ISP1362 Interrupt 1
109 input iOTG_DREQ0, // ISP1362 DMA Request 0
110 input iOTG_DREQ1, // ISP1362 DMA Request 1
111 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
112 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
113 //////////////////// LCD Module 16X2 ////////////////////////////
114 inout [7:0] LCD_D, // LCD Data bus 8 bits
115 output oLCD_ON, // LCD Power ON/OFF
116 output oLCD_BLON, // LCD Back Light ON/OFF
117 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
118 output oLCD_EN, // LCD Enable
119 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
120 //////////////////// SD Card Interface ////////////////////////
121 inout SD_DAT, // SD Card Data
122 inout SD_DAT3, // SD Card Data 3
123 inout SD_CMD, // SD Card Command Signal
124 output oSD_CLK, // SD Card Clock
125 //////////////////////// I2C ////////////////////////////////
126 inout I2C_SDAT, // I2C Data
127 output oI2C_SCLK, // I2C Clock
128 //////////////////////// PS2 ////////////////////////////////
129 inout PS2_KBDAT, // PS2 Keyboard Data
130 inout PS2_KBCLK, // PS2 Keyboard Clock
131 inout PS2_MSDAT, // PS2 Mouse Data
132 inout PS2_MSCLK, // PS2 Mouse Clock
133 //////////////////////// VGA ////////////////////////////
134 output oVGA_CLOCK, // VGA Clock
135 output oVGA_HS, // VGA H_SYNC
136 output oVGA_VS, // VGA V_SYNC
137 output oVGA_BLANK_N, // VGA BLANK
138 output oVGA_SYNC_N, // VGA SYNC
139 output [9:0] oVGA_R, // VGA Red[9:0]
140 output [9:0] oVGA_G, // VGA Green[9:0]
141 output [9:0] oVGA_B, // VGA Blue[9:0]
142 //////////////// Ethernet Interface ////////////////////////////
143 inout [15:0] ENET_D, // DM9000A DATA bus 16Bits
144 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
145 output oENET_CS_N, // DM9000A Chip Select
146 output oENET_IOW_N, // DM9000A Write
147 output oENET_IOR_N, // DM9000A Read
148 output oENET_RESET_N, // DM9000A Reset
149 input iENET_INT, // DM9000A Interrupt
150 output oENET_CLK, // DM9000A Clock 25 MHz
151 //////////////////// Audio CODEC ////////////////////////////
152 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
153 input iAUD_ADCDAT, // Audio CODEC ADC Data
154 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
155 output oAUD_DACDAT, // Audio CODEC DAC Data
156 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
157 output oAUD_XCK, // Audio CODEC Chip Clock
158 //////////////////// TV Devoder ////////////////////////////
159 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
160 input [7:0] iTD1_D, // TV Decoder1 Data bus 8 bits
161 input iTD1_HS, // TV Decoder1 H_SYNC
162 input iTD1_VS, // TV Decoder1 V_SYNC
163 output oTD1_RESET_N, // TV Decoder1 Reset
164 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
165 input [7:0] iTD2_D, // TV Decoder2 Data bus 8 bits
166 input iTD2_HS, // TV Decoder2 H_SYNC
167 input iTD2_VS, // TV Decoder2 V_SYNC
168 output oTD2_RESET_N, // TV Decoder2 Reset
169 //////////////////////// GPIO ////////////////////////////////
170 inout [31:0] GPIO_0, // GPIO Connection 0 I/O
171 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
172 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
173 inout GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
174 inout GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
175 inout [31:0] GPIO_1, // GPIO Connection 1 I/O
176 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
177 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
178 inout GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
179 inout GPIO_CLKOUT_P1 // GPIO Connection 1 Clock Output 1
180 );
181
182 // CCD
183 wire [11:0] CCD_DATA;
184 wire CCD_SDAT;
185 wire CCD_SCLK;
186 wire CCD_FLASH;
187 wire CCD_FVAL;
188 wire CCD_LVAL;
189 wire CCD_PIXCLK;
190 wire CCD_MCLK; // CCD Master Clock
191
192 wire [15:0] Read_DATA1;
193 wire [15:0] Read_DATA2;
194 wire VGA_CTRL_CLK;
195 wire [11:0] mCCD_DATA;
196 wire mCCD_DVAL;
197 wire mCCD_DVAL_d;
198 wire [15:0] X_Cont;
199 wire [15:0] Y_Cont;
200 wire [9:0] X_ADDR;
201 wire [31:0] Frame_Cont;
202 wire DLY_RST_0;
203 wire DLY_RST_1;
204 wire DLY_RST_2;
205 wire Read;
206 reg [11:0] rCCD_DATA;
207 reg rCCD_LVAL;
208 reg rCCD_FVAL;
209 wire [11:0] sCCD_R;
210 wire [11:0] sCCD_G;
211 wire [11:0] sCCD_B;
212 wire sCCD_DVAL;
213 reg [1:0] rClk;
214 wire sdram_ctrl_clk;
215
216 // Touch panel signal
217 wire [7:0] ltm_r; // LTM Red Data 8 Bits
218 wire [7:0] ltm_g; // LTM Green Data 8 Bits
219 wire [7:0] ltm_b; // LTM Blue Data 8 Bits
220 wire ltm_nclk; // LTM Clcok
221 wire ltm_hd;
222 wire ltm_vd;
223 wire ltm_den;
224 wire adc_dclk;
225 wire adc_cs;
226 wire adc_penirq_n;
227 wire adc_busy;
228 wire adc_din;
229 wire adc_dout;
230 wire adc_ltm_sclk;
231 wire ltm_grst;
232
233 // LTM Config
234 wire ltm_sclk;
235 wire ltm_sda;
236 wire ltm_scen;
237 wire ltm_3wirebusy_n;
238
239 assign CCD_DATA[0] = GPIO_1[11];
240 assign CCD_DATA[1] = GPIO_1[10];
241 assign CCD_DATA[2] = GPIO_1[9];
242 assign CCD_DATA[3] = GPIO_1[8];
243 assign CCD_DATA[4] = GPIO_1[7];
244 assign CCD_DATA[5] = GPIO_1[6];
245 assign CCD_DATA[6] = GPIO_1[5];
246 assign CCD_DATA[7] = GPIO_1[4];
247 assign CCD_DATA[8] = GPIO_1[3];
248 assign CCD_DATA[9] = GPIO_1[2];
249 assign CCD_DATA[10] = GPIO_1[1];
250 assign CCD_DATA[11] = GPIO_1[0];
251 assign GPIO_CLKOUT_N1 = CCD_MCLK;
252 assign CCD_FVAL = GPIO_1[18];
253 assign CCD_LVAL = GPIO_1[17];
254 assign CCD_PIXCLK = GPIO_CLKIN_N1;
255 assign GPIO_1[15] = 1'b1; // tRIGGER
256 assign GPIO_1[14] = DLY_RST_1;
257
258 assign oLEDR = iSW;
259 assign oLEDG = Y_Cont;
260
261 assign oTD1_RESET_N = 1'b1;
262 assign oVGA_CLOCK = ~VGA_CTRL_CLK;
263
264 assign CCD_MCLK = rClk[0];
265 assign oUART_TXD = iUART_RXD;
266
267 assign adc_penirq_n = GPIO_CLKIN_N0;
268 assign adc_dout = GPIO_0[0];
269 assign adc_busy = GPIO_CLKIN_P0;
270 assign GPIO_0[1] = adc_din;
271 assign GPIO_0[2] = adc_ltm_sclk;
272 assign GPIO_0[3] = ltm_b[3];
273 assign GPIO_0[4] = ltm_b[2];
274 assign GPIO_0[5] = ltm_b[1];
275 assign GPIO_0[6] = ltm_b[0];
276 assign GPIO_0[7] =~ltm_nclk;
277 assign GPIO_0[8] = ltm_den;
278 assign GPIO_0[9] = ltm_hd;
279 assign GPIO_0[10] = ltm_vd;
280 assign GPIO_0[11] = ltm_b[4];
281 assign GPIO_0[12] = ltm_b[5];
282 assign GPIO_0[13] = ltm_b[6];
283 assign GPIO_CLKOUT_N0 = ltm_b[7];
284 assign GPIO_0[14] = ltm_g[0];
285 assign GPIO_CLKOUT_P0 = ltm_g[1];
286 assign GPIO_0[15] = ltm_g[2];
287 assign GPIO_0[16] = ltm_g[3];
288 assign GPIO_0[17] = ltm_g[4];
289 assign GPIO_0[18] = ltm_g[5];
290 assign GPIO_0[19] = ltm_g[6];
291 assign GPIO_0[20] = ltm_g[7];
292 assign GPIO_0[21] = ltm_r[0];
293 assign GPIO_0[22] = ltm_r[1];
294 assign GPIO_0[23] = ltm_r[2];
295 assign GPIO_0[24] = ltm_r[3];
296 assign GPIO_0[25] = ltm_r[4];
297 assign GPIO_0[26] = ltm_r[5];
298 assign GPIO_0[27] = ltm_r[6];
299 assign GPIO_0[28] = ltm_r[7];
300 assign GPIO_0[29] = ltm_grst;
301 assign GPIO_0[30] = ltm_scen;
302 assign GPIO_0[31] = ltm_sda;
303
304 assign ltm_grst = iKEY[0];
305 assign adc_ltm_sclk = ltm_sclk;
306
307 assign ltm_r = ltm_g;
308 assign ltm_b = ltm_g;
309
310 Reset_Delay reset0 (
311 .iCLK(iCLK_50),
312 .iRST(iKEY[0]),
313 .oRST_0(DLY_RST_0),
314 .oRST_1(DLY_RST_1),
315 .oRST_2(DLY_RST_2)
316 );
317
318 CCD_Capture capture0 (
319 .oDATA(mCCD_DATA),
320 .oDVAL(mCCD_DVAL),
321 .oX_Cont(X_Cont),
322 .oY_Cont(Y_Cont),
323 .oFrame_Cont(Frame_Cont),
324 .iDATA(rCCD_DATA),
325 .iFVAL(rCCD_FVAL),
326 .iLVAL(rCCD_LVAL),
327 .iSTART(!iKEY[3]),
328 .iEND(!iKEY[2]),
329 .iCLK(CCD_PIXCLK),
330 .iRST(DLY_RST_2)
331 );
332
333 RAW2RGB rgb0 (
334 .iCLK(CCD_PIXCLK),
335 .iRST_n(DLY_RST_1),
336 .iData(mCCD_DATA),
337 .iDval(mCCD_DVAL),
338 .oRed(sCCD_R),
339 .oGreen(sCCD_G),
340 .oBlue(sCCD_B),
341 .oDval(sCCD_DVAL),
342 .iMIRROR(iSW[17]),
343 .iX_Cont(X_Cont),
344 .iY_Cont(Y_Cont)
345 );
346
347 SEG7_LUT_8 seg0 (
348 .oSEG0(oHEX0_D),
349 .oSEG1(oHEX1_D),
350 .oSEG2(oHEX2_D),
351 .oSEG3(oHEX3_D),
352 .oSEG4(oHEX4_D),
353 .oSEG5(oHEX5_D),
354 .oSEG6(oHEX6_D),
355 .oSEG7(oHEX7_D),
356 .iDIG(Frame_Cont[31:0])
357 );
358
359 vga_pll vga_pll0 (
360 .inclk0(iCLK_50_2),
361 .c0(ltm_nclk)
362 );
363
364 sdram_pll sdram_pll0 (
365 .inclk0(iCLK_50_3),
366 .c0(sdram_ctrl_clk),
367 .c1(oDRAM0_CLK),
368 .c2(oDRAM1_CLK)
369 );
370
371 Sdram_Control_4Port sdram0 (
372 // HOST Side
373 .REF_CLK(iCLK_50),
374 .RESET_N(1'b1),
375 .CLK(sdram_ctrl_clk),
376 // FIFO Write Side 1
377 .WR1_DATA({sCCD_G[11:7], sCCD_B[11:2]}),
378 .WR1(sCCD_DVAL),
379 .WR1_ADDR(0),
380 .WR1_MAX_ADDR(800*480),
381 .WR1_LENGTH(9'h100),
382 .WR1_LOAD(!DLY_RST_0),
383 .WR1_CLK(CCD_PIXCLK),
384 // FIFO Read Side 1
385 .RD1_DATA(Read_DATA1),
386 .RD1(Read),
387 .RD1_ADDR(0),
388 .RD1_MAX_ADDR(800*480),
389 .RD1_LENGTH(9'h100),
390 .RD1_LOAD(!DLY_RST_0),
391 .RD1_CLK(~ltm_nclk),
392 // SDRAM Side
393 .SA(oDRAM0_A[11:0]),
394 .BA(oDRAM0_BA),
395 .CS_N(oDRAM0_CS_N),
396 .CKE(oDRAM0_CKE),
397 .RAS_N(oDRAM0_RAS_N),
398 .CAS_N(oDRAM0_CAS_N),
399 .WE_N(oDRAM0_WE_N),
400 .DQ(DRAM_DQ[15:0]),
401 .DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
402 );
403
404 Sdram_Control_4Port sdram1 (
405 // HOST Side
406 .REF_CLK(iCLK_50),
407 .RESET_N(1'b1),
408 .CLK(sdram_ctrl_clk),
409 // FIFO Write Side 1
410 .WR1_DATA({sCCD_G[6:2], sCCD_R[11:2]}),
411 .WR1(sCCD_DVAL),
412 .WR1_ADDR(0),
413 .WR1_MAX_ADDR(800*480),
414 .WR1_LENGTH(9'h100),
415 .WR1_LOAD(!DLY_RST_0),
416 .WR1_CLK(CCD_PIXCLK),
417 // FIFO Read Side 1
418 .RD1_DATA(Read_DATA2),
419 .RD1(Read),
420 .RD1_ADDR(0),
421 .RD1_MAX_ADDR(800*480),
422 .RD1_LENGTH(9'h100),
423 .RD1_LOAD(!DLY_RST_0),
424 .RD1_CLK(~ltm_nclk),
425 // SDRAM Side
426 .SA(oDRAM1_A[11:0]),
427 .BA(oDRAM1_BA),
428 .CS_N(oDRAM1_CS_N),
429 .CKE(oDRAM1_CKE),
430 .RAS_N(oDRAM1_RAS_N),
431 .CAS_N(oDRAM1_CAS_N),
432 .WE_N(oDRAM1_WE_N),
433 .DQ(DRAM_DQ[31:16]),
434 .DQM({oDRAM1_UDQM1,oDRAM1_LDQM0})
435 );
436
437 I2C_CCD_Config ccd_config0 (
438 // Host Side
439 .iCLK(iCLK_50),
440 .iRST_N(DLY_RST_1),
441 .iEXPOSURE_ADJ(iKEY[1]),
442 .iEXPOSURE_DEC_p(iSW[0]),
443 .iMIRROR_SW(iSW[17]),
444 // I2C Side
445 .I2C_SCLK(GPIO_1[20]),
446 .I2C_SDAT(GPIO_1[19])
447 );
448
449 touch_tcon tcon0 (
450 .iCLK(ltm_nclk),
451 .iRST_n(DLY_RST_2),
452 // sdram side
453 .iREAD_DATA1(Read_DATA1),
454 .iREAD_DATA2(Read_DATA2),
455 .oREAD_SDRAM_EN(Read),
456 // lcd side
457 .oLCD_G(ltm_g),
458 .oHD(ltm_hd),
459 .oVD(ltm_vd),
460 .oDEN(ltm_den)
461 );
462
463 lcd_3wire_config wire0 (
464 // Host Side
465 .iCLK(iCLK_50),
466 .iRST_n(DLY_RST_0),
467 // 3 wire Side
468 .o3WIRE_SCLK(ltm_sclk),
469 .io3WIRE_SDAT(ltm_sda),
470 .o3WIRE_SCEN(ltm_scen),
471 .o3WIRE_BUSY_n(ltm_3wirebusy_n)
472 );
473
474 always@(posedge iCLK_50)
475 rClk <= rClk + 1;
476
477 always@(posedge CCD_PIXCLK) begin
478 rCCD_DATA <= CCD_DATA;
479 rCCD_LVAL <= CCD_LVAL;
480 rCCD_FVAL <= CCD_FVAL;
481 end
482
483 endmodule
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : DE2_70.v
5 Compiler : Quartus II 7.2 SP3
6 Description : Demo how to use TRDB-D5M with LTM to make gray on DE2-70 after SDRAM
7 Release : 08/23/2008 1.0
8 */
9
10 module DE2_70 (
11 //////////////////////// Clock Input ////////////////////////
12 input iCLK_28, // 28.63636 MHz
13 input iCLK_50, // 50 MHz
14 input iCLK_50_2, // 50 MHz
15 input iCLK_50_3, // 50 MHz
16 input iCLK_50_4, // 50 MHz
17 input iEXT_CLOCK, // External Clock
18 //////////////////////// Push Button ////////////////////////
19 input [3:0] iKEY, // Pushbutton[3:0]
20 //////////////////////// DPDT Switch ////////////////////////
21 input [17:0] iSW, // Toggle Switch[17:0]
22 //////////////////////// 7-SEG Dispaly ////////////////////////
23 output [6:0] oHEX0_D, // Seven Segment Digit 0
24 output oHEX0_DP, // Seven Segment Digit 0 decimal point
25 output [6:0] oHEX1_D, // Seven Segment Digit 1
26 output oHEX1_DP, // Seven Segment Digit 1 decimal point
27 output [6:0] oHEX2_D, // Seven Segment Digit 2
28 output oHEX2_DP, // Seven Segment Digit 2 decimal point
29 output [6:0] oHEX3_D, // Seven Segment Digit 3
30 output oHEX3_DP, // Seven Segment Digit 3 decimal point
31 output [6:0] oHEX4_D, // Seven Segment Digit 4
32 output oHEX4_DP, // Seven Segment Digit 4 decimal point
33 output [6:0] oHEX5_D, // Seven Segment Digit 5
34 output oHEX5_DP, // Seven Segment Digit 5 decimal point
35 output [6:0] oHEX6_D, // Seven Segment Digit 6
36 output oHEX6_DP, // Seven Segment Digit 6 decimal point
37 output [6:0] oHEX7_D, // Seven Segment Digit 7
38 output oHEX7_DP, // Seven Segment Digit 7 decimal point
39 //////////////////////////// LED ////////////////////////////
40 output [8:0] oLEDG, // LED Green[8:0]
41 output [17:0] oLEDR, // LED Red[17:0]
42 //////////////////////////// UART ////////////////////////////
43 output oUART_TXD, // UART Transmitter
44 input iUART_RXD, // UART Receiver
45 output oUART_CTS, // UART Clear To Send
46 input iUART_RTS, // UART Requst To Send
47 //////////////////////////// IRDA ////////////////////////////
48 output oIRDA_TXD, // IRDA Transmitter
49 input iIRDA_RXD, // IRDA Receiver
50 /////////////////////// SDRAM Interface ////////////////////////
51 inout [31:0] DRAM_DQ, // SDRAM Data bus 32 Bits
52 output [12:0] oDRAM0_A, // SDRAM0 Address bus 13 Bits
53 output [12:0] oDRAM1_A, // SDRAM1 Address bus 13 Bits
54 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
55 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
56 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
57 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
58 output oDRAM0_WE_N, // SDRAM0 Write Enable
59 output oDRAM1_WE_N, // SDRAM1 Write Enable
60 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
61 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
62 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
63 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
64 output oDRAM0_CS_N, // SDRAM0 Chip Select
65 output oDRAM1_CS_N, // SDRAM1 Chip Select
66 output [1:0] oDRAM0_BA, // SDRAM0 Bank Address
67 output [1:0] oDRAM1_BA, // SDRAM1 Bank Address
68 output oDRAM0_CLK, // SDRAM0 Clock
69 output oDRAM1_CLK, // SDRAM1 Clock
70 output oDRAM0_CKE, // SDRAM0 Clock Enable
71 output oDRAM1_CKE, // SDRAM1 Clock Enable
72 //////////////////////// Flash Interface ////////////////////////
73 inout [14:0] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
74 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
75 output [21:0] oFLASH_A, // FLASH Address bus 26 Bits
76 output oFLASH_WE_N, // FLASH Write Enable
77 output oFLASH_RST_N, // FLASH Reset
78 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
79 input iFLASH_RY_N, // FLASH Ready/Busy output
80 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
81 output oFLASH_OE_N, // FLASH Output Enable
82 output oFLASH_CE_N, // FLASH Chip Enable
83 //////////////////////// SRAM Interface ////////////////////////
84 inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
85 inout [3:0] SRAM_DPA, // SRAM Parity Data Bus
86 output [18:0] oSRAM_A, // SRAM Address bus 21 Bits
87 output oSRAM_ADSC_N, // SRAM Controller Address Status
88 output oSRAM_ADSP_N, // SRAM Processor Address Status
89 output oSRAM_ADV_N, // SRAM Burst Address Advance
90 output [3:0] oSRAM_BE_N, // SRAM Byte Write Enable
91 output oSRAM_CE1_N, // SRAM Chip Enable
92 output oSRAM_CE2, // SRAM Chip Enable
93 output oSRAM_CE3_N, // SRAM Chip Enable
94 output oSRAM_CLK, // SRAM Clock
95 output oSRAM_GW_N, // SRAM Global Write Enable
96 output oSRAM_OE_N, // SRAM Output Enable
97 output oSRAM_WE_N, // SRAM Write Enable
98 //////////////////// ISP1362 Interface ////////////////////////
99 inout [15:0] OTG_D, // ISP1362 Data bus 16 Bits
100 output [1:0] oOTG_A, // ISP1362 Address 2 Bits
101 output oOTG_CS_N, // ISP1362 Chip Select
102 output oOTG_OE_N, // ISP1362 Read
103 output oOTG_WE_N, // ISP1362 Write
104 output oOTG_RESET_N, // ISP1362 Reset
105 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
106 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
107 input iOTG_INT0, // ISP1362 Interrupt 0
108 input iOTG_INT1, // ISP1362 Interrupt 1
109 input iOTG_DREQ0, // ISP1362 DMA Request 0
110 input iOTG_DREQ1, // ISP1362 DMA Request 1
111 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
112 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
113 //////////////////// LCD Module 16X2 ////////////////////////////
114 inout [7:0] LCD_D, // LCD Data bus 8 bits
115 output oLCD_ON, // LCD Power ON/OFF
116 output oLCD_BLON, // LCD Back Light ON/OFF
117 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
118 output oLCD_EN, // LCD Enable
119 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
120 //////////////////// SD Card Interface ////////////////////////
121 inout SD_DAT, // SD Card Data
122 inout SD_DAT3, // SD Card Data 3
123 inout SD_CMD, // SD Card Command Signal
124 output oSD_CLK, // SD Card Clock
125 //////////////////////// I2C ////////////////////////////////
126 inout I2C_SDAT, // I2C Data
127 output oI2C_SCLK, // I2C Clock
128 //////////////////////// PS2 ////////////////////////////////
129 inout PS2_KBDAT, // PS2 Keyboard Data
130 inout PS2_KBCLK, // PS2 Keyboard Clock
131 inout PS2_MSDAT, // PS2 Mouse Data
132 inout PS2_MSCLK, // PS2 Mouse Clock
133 //////////////////////// VGA ////////////////////////////
134 output oVGA_CLOCK, // VGA Clock
135 output oVGA_HS, // VGA H_SYNC
136 output oVGA_VS, // VGA V_SYNC
137 output oVGA_BLANK_N, // VGA BLANK
138 output oVGA_SYNC_N, // VGA SYNC
139 output [9:0] oVGA_R, // VGA Red[9:0]
140 output [9:0] oVGA_G, // VGA Green[9:0]
141 output [9:0] oVGA_B, // VGA Blue[9:0]
142 //////////////// Ethernet Interface ////////////////////////////
143 inout [15:0] ENET_D, // DM9000A DATA bus 16Bits
144 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
145 output oENET_CS_N, // DM9000A Chip Select
146 output oENET_IOW_N, // DM9000A Write
147 output oENET_IOR_N, // DM9000A Read
148 output oENET_RESET_N, // DM9000A Reset
149 input iENET_INT, // DM9000A Interrupt
150 output oENET_CLK, // DM9000A Clock 25 MHz
151 //////////////////// Audio CODEC ////////////////////////////
152 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
153 input iAUD_ADCDAT, // Audio CODEC ADC Data
154 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
155 output oAUD_DACDAT, // Audio CODEC DAC Data
156 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
157 output oAUD_XCK, // Audio CODEC Chip Clock
158 //////////////////// TV Devoder ////////////////////////////
159 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
160 input [7:0] iTD1_D, // TV Decoder1 Data bus 8 bits
161 input iTD1_HS, // TV Decoder1 H_SYNC
162 input iTD1_VS, // TV Decoder1 V_SYNC
163 output oTD1_RESET_N, // TV Decoder1 Reset
164 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
165 input [7:0] iTD2_D, // TV Decoder2 Data bus 8 bits
166 input iTD2_HS, // TV Decoder2 H_SYNC
167 input iTD2_VS, // TV Decoder2 V_SYNC
168 output oTD2_RESET_N, // TV Decoder2 Reset
169 //////////////////////// GPIO ////////////////////////////////
170 inout [31:0] GPIO_0, // GPIO Connection 0 I/O
171 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
172 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
173 inout GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
174 inout GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
175 inout [31:0] GPIO_1, // GPIO Connection 1 I/O
176 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
177 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
178 inout GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
179 inout GPIO_CLKOUT_P1 // GPIO Connection 1 Clock Output 1
180 );
181
182 // CCD
183 wire [11:0] CCD_DATA;
184 wire CCD_SDAT;
185 wire CCD_SCLK;
186 wire CCD_FLASH;
187 wire CCD_FVAL;
188 wire CCD_LVAL;
189 wire CCD_PIXCLK;
190 wire CCD_MCLK; // CCD Master Clock
191
192 wire [15:0] Read_DATA1;
193 wire [15:0] Read_DATA2;
194 wire VGA_CTRL_CLK;
195 wire [11:0] mCCD_DATA;
196 wire mCCD_DVAL;
197 wire mCCD_DVAL_d;
198 wire [15:0] X_Cont;
199 wire [15:0] Y_Cont;
200 wire [9:0] X_ADDR;
201 wire [31:0] Frame_Cont;
202 wire DLY_RST_0;
203 wire DLY_RST_1;
204 wire DLY_RST_2;
205 wire Read;
206 reg [11:0] rCCD_DATA;
207 reg rCCD_LVAL;
208 reg rCCD_FVAL;
209 wire [11:0] sCCD_R;
210 wire [11:0] sCCD_G;
211 wire [11:0] sCCD_B;
212 wire sCCD_DVAL;
213 reg [1:0] rClk;
214 wire sdram_ctrl_clk;
215
216 // Touch panel signal
217 wire [7:0] ltm_r; // LTM Red Data 8 Bits
218 wire [7:0] ltm_g; // LTM Green Data 8 Bits
219 wire [7:0] ltm_b; // LTM Blue Data 8 Bits
220 wire ltm_nclk; // LTM Clcok
221 wire ltm_hd;
222 wire ltm_vd;
223 wire ltm_den;
224 wire adc_dclk;
225 wire adc_cs;
226 wire adc_penirq_n;
227 wire adc_busy;
228 wire adc_din;
229 wire adc_dout;
230 wire adc_ltm_sclk;
231 wire ltm_grst;
232
233 // LTM Config
234 wire ltm_sclk;
235 wire ltm_sda;
236 wire ltm_scen;
237 wire ltm_3wirebusy_n;
238
239 assign CCD_DATA[0] = GPIO_1[11];
240 assign CCD_DATA[1] = GPIO_1[10];
241 assign CCD_DATA[2] = GPIO_1[9];
242 assign CCD_DATA[3] = GPIO_1[8];
243 assign CCD_DATA[4] = GPIO_1[7];
244 assign CCD_DATA[5] = GPIO_1[6];
245 assign CCD_DATA[6] = GPIO_1[5];
246 assign CCD_DATA[7] = GPIO_1[4];
247 assign CCD_DATA[8] = GPIO_1[3];
248 assign CCD_DATA[9] = GPIO_1[2];
249 assign CCD_DATA[10] = GPIO_1[1];
250 assign CCD_DATA[11] = GPIO_1[0];
251 assign GPIO_CLKOUT_N1 = CCD_MCLK;
252 assign CCD_FVAL = GPIO_1[18];
253 assign CCD_LVAL = GPIO_1[17];
254 assign CCD_PIXCLK = GPIO_CLKIN_N1;
255 assign GPIO_1[15] = 1'b1; // tRIGGER
256 assign GPIO_1[14] = DLY_RST_1;
257
258 assign oLEDR = iSW;
259 assign oLEDG = Y_Cont;
260
261 assign oTD1_RESET_N = 1'b1;
262 assign oVGA_CLOCK = ~VGA_CTRL_CLK;
263
264 assign CCD_MCLK = rClk[0];
265 assign oUART_TXD = iUART_RXD;
266
267 assign adc_penirq_n = GPIO_CLKIN_N0;
268 assign adc_dout = GPIO_0[0];
269 assign adc_busy = GPIO_CLKIN_P0;
270 assign GPIO_0[1] = adc_din;
271 assign GPIO_0[2] = adc_ltm_sclk;
272 assign GPIO_0[3] = ltm_b[3];
273 assign GPIO_0[4] = ltm_b[2];
274 assign GPIO_0[5] = ltm_b[1];
275 assign GPIO_0[6] = ltm_b[0];
276 assign GPIO_0[7] =~ltm_nclk;
277 assign GPIO_0[8] = ltm_den;
278 assign GPIO_0[9] = ltm_hd;
279 assign GPIO_0[10] = ltm_vd;
280 assign GPIO_0[11] = ltm_b[4];
281 assign GPIO_0[12] = ltm_b[5];
282 assign GPIO_0[13] = ltm_b[6];
283 assign GPIO_CLKOUT_N0 = ltm_b[7];
284 assign GPIO_0[14] = ltm_g[0];
285 assign GPIO_CLKOUT_P0 = ltm_g[1];
286 assign GPIO_0[15] = ltm_g[2];
287 assign GPIO_0[16] = ltm_g[3];
288 assign GPIO_0[17] = ltm_g[4];
289 assign GPIO_0[18] = ltm_g[5];
290 assign GPIO_0[19] = ltm_g[6];
291 assign GPIO_0[20] = ltm_g[7];
292 assign GPIO_0[21] = ltm_r[0];
293 assign GPIO_0[22] = ltm_r[1];
294 assign GPIO_0[23] = ltm_r[2];
295 assign GPIO_0[24] = ltm_r[3];
296 assign GPIO_0[25] = ltm_r[4];
297 assign GPIO_0[26] = ltm_r[5];
298 assign GPIO_0[27] = ltm_r[6];
299 assign GPIO_0[28] = ltm_r[7];
300 assign GPIO_0[29] = ltm_grst;
301 assign GPIO_0[30] = ltm_scen;
302 assign GPIO_0[31] = ltm_sda;
303
304 assign ltm_grst = iKEY[0];
305 assign adc_ltm_sclk = ltm_sclk;
306
307 assign ltm_r = ltm_g;
308 assign ltm_b = ltm_g;
309
310 Reset_Delay reset0 (
311 .iCLK(iCLK_50),
312 .iRST(iKEY[0]),
313 .oRST_0(DLY_RST_0),
314 .oRST_1(DLY_RST_1),
315 .oRST_2(DLY_RST_2)
316 );
317
318 CCD_Capture capture0 (
319 .oDATA(mCCD_DATA),
320 .oDVAL(mCCD_DVAL),
321 .oX_Cont(X_Cont),
322 .oY_Cont(Y_Cont),
323 .oFrame_Cont(Frame_Cont),
324 .iDATA(rCCD_DATA),
325 .iFVAL(rCCD_FVAL),
326 .iLVAL(rCCD_LVAL),
327 .iSTART(!iKEY[3]),
328 .iEND(!iKEY[2]),
329 .iCLK(CCD_PIXCLK),
330 .iRST(DLY_RST_2)
331 );
332
333 RAW2RGB rgb0 (
334 .iCLK(CCD_PIXCLK),
335 .iRST_n(DLY_RST_1),
336 .iData(mCCD_DATA),
337 .iDval(mCCD_DVAL),
338 .oRed(sCCD_R),
339 .oGreen(sCCD_G),
340 .oBlue(sCCD_B),
341 .oDval(sCCD_DVAL),
342 .iMIRROR(iSW[17]),
343 .iX_Cont(X_Cont),
344 .iY_Cont(Y_Cont)
345 );
346
347 SEG7_LUT_8 seg0 (
348 .oSEG0(oHEX0_D),
349 .oSEG1(oHEX1_D),
350 .oSEG2(oHEX2_D),
351 .oSEG3(oHEX3_D),
352 .oSEG4(oHEX4_D),
353 .oSEG5(oHEX5_D),
354 .oSEG6(oHEX6_D),
355 .oSEG7(oHEX7_D),
356 .iDIG(Frame_Cont[31:0])
357 );
358
359 vga_pll vga_pll0 (
360 .inclk0(iCLK_50_2),
361 .c0(ltm_nclk)
362 );
363
364 sdram_pll sdram_pll0 (
365 .inclk0(iCLK_50_3),
366 .c0(sdram_ctrl_clk),
367 .c1(oDRAM0_CLK),
368 .c2(oDRAM1_CLK)
369 );
370
371 Sdram_Control_4Port sdram0 (
372 // HOST Side
373 .REF_CLK(iCLK_50),
374 .RESET_N(1'b1),
375 .CLK(sdram_ctrl_clk),
376 // FIFO Write Side 1
377 .WR1_DATA({sCCD_G[11:7], sCCD_B[11:2]}),
378 .WR1(sCCD_DVAL),
379 .WR1_ADDR(0),
380 .WR1_MAX_ADDR(800*480),
381 .WR1_LENGTH(9'h100),
382 .WR1_LOAD(!DLY_RST_0),
383 .WR1_CLK(CCD_PIXCLK),
384 // FIFO Read Side 1
385 .RD1_DATA(Read_DATA1),
386 .RD1(Read),
387 .RD1_ADDR(0),
388 .RD1_MAX_ADDR(800*480),
389 .RD1_LENGTH(9'h100),
390 .RD1_LOAD(!DLY_RST_0),
391 .RD1_CLK(~ltm_nclk),
392 // SDRAM Side
393 .SA(oDRAM0_A[11:0]),
394 .BA(oDRAM0_BA),
395 .CS_N(oDRAM0_CS_N),
396 .CKE(oDRAM0_CKE),
397 .RAS_N(oDRAM0_RAS_N),
398 .CAS_N(oDRAM0_CAS_N),
399 .WE_N(oDRAM0_WE_N),
400 .DQ(DRAM_DQ[15:0]),
401 .DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
402 );
403
404 Sdram_Control_4Port sdram1 (
405 // HOST Side
406 .REF_CLK(iCLK_50),
407 .RESET_N(1'b1),
408 .CLK(sdram_ctrl_clk),
409 // FIFO Write Side 1
410 .WR1_DATA({sCCD_G[6:2], sCCD_R[11:2]}),
411 .WR1(sCCD_DVAL),
412 .WR1_ADDR(0),
413 .WR1_MAX_ADDR(800*480),
414 .WR1_LENGTH(9'h100),
415 .WR1_LOAD(!DLY_RST_0),
416 .WR1_CLK(CCD_PIXCLK),
417 // FIFO Read Side 1
418 .RD1_DATA(Read_DATA2),
419 .RD1(Read),
420 .RD1_ADDR(0),
421 .RD1_MAX_ADDR(800*480),
422 .RD1_LENGTH(9'h100),
423 .RD1_LOAD(!DLY_RST_0),
424 .RD1_CLK(~ltm_nclk),
425 // SDRAM Side
426 .SA(oDRAM1_A[11:0]),
427 .BA(oDRAM1_BA),
428 .CS_N(oDRAM1_CS_N),
429 .CKE(oDRAM1_CKE),
430 .RAS_N(oDRAM1_RAS_N),
431 .CAS_N(oDRAM1_CAS_N),
432 .WE_N(oDRAM1_WE_N),
433 .DQ(DRAM_DQ[31:16]),
434 .DQM({oDRAM1_UDQM1,oDRAM1_LDQM0})
435 );
436
437 I2C_CCD_Config ccd_config0 (
438 // Host Side
439 .iCLK(iCLK_50),
440 .iRST_N(DLY_RST_1),
441 .iEXPOSURE_ADJ(iKEY[1]),
442 .iEXPOSURE_DEC_p(iSW[0]),
443 .iMIRROR_SW(iSW[17]),
444 // I2C Side
445 .I2C_SCLK(GPIO_1[20]),
446 .I2C_SDAT(GPIO_1[19])
447 );
448
449 touch_tcon tcon0 (
450 .iCLK(ltm_nclk),
451 .iRST_n(DLY_RST_2),
452 // sdram side
453 .iREAD_DATA1(Read_DATA1),
454 .iREAD_DATA2(Read_DATA2),
455 .oREAD_SDRAM_EN(Read),
456 // lcd side
457 .oLCD_G(ltm_g),
458 .oHD(ltm_hd),
459 .oVD(ltm_vd),
460 .oDEN(ltm_den)
461 );
462
463 lcd_3wire_config wire0 (
464 // Host Side
465 .iCLK(iCLK_50),
466 .iRST_n(DLY_RST_0),
467 // 3 wire Side
468 .o3WIRE_SCLK(ltm_sclk),
469 .io3WIRE_SDAT(ltm_sda),
470 .o3WIRE_SCEN(ltm_scen),
471 .o3WIRE_BUSY_n(ltm_3wirebusy_n)
472 );
473
474 always@(posedge iCLK_50)
475 rClk <= rClk + 1;
476
477 always@(posedge CCD_PIXCLK) begin
478 rCCD_DATA <= CCD_DATA;
479 rCCD_LVAL <= CCD_LVAL;
480 rCCD_FVAL <= CCD_FVAL;
481 end
482
483 endmodule
449行
touch_tcon tcon0 (
.iCLK(ltm_nclk),
.iRST_n(DLY_RST_2),
// sdram side
.iREAD_DATA1(Read_DATA1),
.iREAD_DATA2(Read_DATA2),
.oREAD_SDRAM_EN(Read),
// lcd side
.oLCD_G(ltm_g),
.oHD(ltm_hd),
.oVD(ltm_vd),
.oDEN(ltm_den)
);
.iCLK(ltm_nclk),
.iRST_n(DLY_RST_2),
// sdram side
.iREAD_DATA1(Read_DATA1),
.iREAD_DATA2(Read_DATA2),
.oREAD_SDRAM_EN(Read),
// lcd side
.oLCD_G(ltm_g),
.oHD(ltm_hd),
.oVD(ltm_vd),
.oDEN(ltm_den)
);
在(原創) 如何Real Time產生灰階影像? (SOC) (DE2) (TRDB-DC2)，我們是在VGA Controller之前處理灰階，不過在DE2-70，在VGA Controller之前處理較麻煩，我們改到VGA Controller之後才處理灰階，只讓touch_tcon輸出ltm_g，而ltm_r與ltm_b並沒有輸出，因為R與B我們打算用G取代。
307行
assign ltm_r = ltm_g;
assign ltm_b = ltm_g;
assign ltm_b = ltm_g;
我們自己來處理ltm_r與ltm_g。
完整程式碼下載
DE2_70_D5M_LTM_before_SDRAM.7z
DE2_70_D5M_LTM_after_SDRAM.7z
Conclusion
談完在DE2與DE2-70實現灰階的方法後，我們將利用此灰階影像，實現Real Time的Sobel Edge Detection。
See Also
(原創) 如何Real Time產生灰階影像? (SOC) (DE2) (TRDB-DC2)
(原創) 如何實現Real Time的Sobel Edge Detector? (SOC) (Verilog) (Image Processing) (DE2-70) (TRDB-D5M)
(原創) 如何實現Real Time的Sobel Edge Detector? (SOC) (Verilog) (Image Processing) (DE2) (TRDB-DC2)
