(原創) 如何解決DE2範例DE2_CCD_detect左右相反的問題? (IC Design) (DE2) (Quartus II)
Abstract
DE2_CCD_detect是友晶科技為DE2和其130萬像素CMOS所寫的motion detection範例，有motion之處會在輸出的VGA顯示紅色，但官方的範例會造成左右相反，本文提出解決的方式。
Introduction
版權聲明：本文根據友晶科技光碟所附的範例程式加以修改，原範例版權歸友晶科技所有。
使用環境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6) + TRDB_DC2
在友晶科技的範例程式光碟中，有兩個有趣的例子，一個是DE2_CCD，展示了130萬像素CMOS基本free run與capture的功能，一個是DE2_CCD_detect，能做real time的motion detection，成果展示可在http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=Taiwan&CategoryNo=38&No=62 觀賞。
DE2_CCD結果正常，DE2_CCD_detect雖然能正確的做出motion detection，但可惜左右相反，經過一番研究，本文提出想種解決方法。
Method 1
這是我寫email問友晶科技(supprt@terasic.com)後，所回覆的官方解法，最簡單也最直接，直接修改I2C_CCD_Config.v。
I2C_CCD_Config.v
1 module I2C_CCD_Config ( // Host Side
2 iCLK,
3 iRST_N,
4 iExposure,
5 // I2C Side
6 I2C_SCLK,
7 I2C_SDAT );
8 // Host Side
9 input iCLK;
10 input iRST_N;
11 input [15:0] iExposure;
12 // I2C Side
13 output I2C_SCLK;
14 inout I2C_SDAT;
15 // Internal Registers/Wires
16 reg [15:0] mI2C_CLK_DIV;
17 reg [23:0] mI2C_DATA;
18 reg mI2C_CTRL_CLK;
19 reg mI2C_GO;
20 wire mI2C_END;
21 wire mI2C_ACK;
22 reg [15:0] LUT_DATA;
23 reg [5:0] LUT_INDEX;
24 reg [3:0] mSetup_ST;
25
26 // Clock Setting
27 parameter CLK_Freq = 50000000; // 50 MHz
28 parameter I2C_Freq = 20000; // 20 KHz
29 // LUT Data Number
30 parameter LUT_SIZE = 17;
31
32 ///////////////////// I2C Control Clock ////////////////////////
33 always@(posedge iCLK or negedge iRST_N)
34 begin
35 if(!iRST_N)
36 begin
37 mI2C_CTRL_CLK <= 0;
38 mI2C_CLK_DIV <= 0;
39 end
40 else
41 begin
42 if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
43 mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
44 else
45 begin
46 mI2C_CLK_DIV <= 0;
47 mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
48 end
49 end
50 end
51 ////////////////////////////////////////////////////////////////////
52 I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
53 .I2C_SCLK(I2C_SCLK), // I2C CLOCK
54 .I2C_SDAT(I2C_SDAT), // I2C DATA
55 .I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
56 .GO(mI2C_GO), // GO transfor
57 .END(mI2C_END), // END transfor
58 .ACK(mI2C_ACK), // ACK
59 .RESET(iRST_N) );
60 ////////////////////////////////////////////////////////////////////
61 ////////////////////// Config Control ////////////////////////////
62 always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
63 begin
64 if(!iRST_N)
65 begin
66 LUT_INDEX <= 0;
67 mSetup_ST <= 0;
68 mI2C_GO <= 0;
69 end
70 else
71 begin
72 if(LUT_INDEX<LUT_SIZE)
73 begin
74 case(mSetup_ST)
75 0: begin
76 mI2C_DATA <= {8'hBA,LUT_DATA};
77 mI2C_GO <= 1;
78 mSetup_ST <= 1;
79 end
80 1: begin
81 if(mI2C_END)
82 begin
83 if(!mI2C_ACK)
84 mSetup_ST <= 2;
85 else
86 mSetup_ST <= 0;
87 mI2C_GO <= 0;
88 end
89 end
90 2: begin
91 LUT_INDEX <= LUT_INDEX+1;
92 mSetup_ST <= 0;
93 end
94 endcase
95 end
96 end
97 end
98 ////////////////////////////////////////////////////////////////////
99 ///////////////////// Config Data LUT //////////////////////////
100 always
101 begin
102 case(LUT_INDEX)
103 0 : LUT_DATA <= 16'h0000;
104 1 : LUT_DATA <= 16'h2000;
105 2 : LUT_DATA <= 16'hF103; // Mirror Row and Columns
106 3 : LUT_DATA <= {8'h09,iExposure[15:8]};// Exposure
107 4 : LUT_DATA <= {8'hF1,iExposure[7:0]};
108 5 : LUT_DATA <= 16'h2B00; // Green 1 Gain
109 6 : LUT_DATA <= 16'hF1B0;
110 7 : LUT_DATA <= 16'h2C00; // Blue Gain
111 8 : LUT_DATA <= 16'hF1CF;
112 9 : LUT_DATA <= 16'h2D00; // Red Gain
113 10 : LUT_DATA <= 16'hF1CF;
114 11 : LUT_DATA <= 16'h2E00; // Green 2 Gain
115 12 : LUT_DATA <= 16'hF1B0;
116 13 : LUT_DATA <= 16'h0500; // H_Blanking
117 14 : LUT_DATA <= 16'hF188;
118 15 : LUT_DATA <= 16'h0600; // V_Blanking
119 16 : LUT_DATA <= 16'hF119;
120 default:LUT_DATA <= 16'h0000;
121 endcase
122 end
123 ////////////////////////////////////////////////////////////////////
124 endmodule
2 iCLK,
3 iRST_N,
4 iExposure,
5 // I2C Side
6 I2C_SCLK,
7 I2C_SDAT );
8 // Host Side
9 input iCLK;
10 input iRST_N;
11 input [15:0] iExposure;
12 // I2C Side
13 output I2C_SCLK;
14 inout I2C_SDAT;
15 // Internal Registers/Wires
16 reg [15:0] mI2C_CLK_DIV;
17 reg [23:0] mI2C_DATA;
18 reg mI2C_CTRL_CLK;
19 reg mI2C_GO;
20 wire mI2C_END;
21 wire mI2C_ACK;
22 reg [15:0] LUT_DATA;
23 reg [5:0] LUT_INDEX;
24 reg [3:0] mSetup_ST;
25
26 // Clock Setting
27 parameter CLK_Freq = 50000000; // 50 MHz
28 parameter I2C_Freq = 20000; // 20 KHz
29 // LUT Data Number
30 parameter LUT_SIZE = 17;
31
32 ///////////////////// I2C Control Clock ////////////////////////
33 always@(posedge iCLK or negedge iRST_N)
34 begin
35 if(!iRST_N)
36 begin
37 mI2C_CTRL_CLK <= 0;
38 mI2C_CLK_DIV <= 0;
39 end
40 else
41 begin
42 if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
43 mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
44 else
45 begin
46 mI2C_CLK_DIV <= 0;
47 mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
48 end
49 end
50 end
51 ////////////////////////////////////////////////////////////////////
52 I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
53 .I2C_SCLK(I2C_SCLK), // I2C CLOCK
54 .I2C_SDAT(I2C_SDAT), // I2C DATA
55 .I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
56 .GO(mI2C_GO), // GO transfor
57 .END(mI2C_END), // END transfor
58 .ACK(mI2C_ACK), // ACK
59 .RESET(iRST_N) );
60 ////////////////////////////////////////////////////////////////////
61 ////////////////////// Config Control ////////////////////////////
62 always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
63 begin
64 if(!iRST_N)
65 begin
66 LUT_INDEX <= 0;
67 mSetup_ST <= 0;
68 mI2C_GO <= 0;
69 end
70 else
71 begin
72 if(LUT_INDEX<LUT_SIZE)
73 begin
74 case(mSetup_ST)
75 0: begin
76 mI2C_DATA <= {8'hBA,LUT_DATA};
77 mI2C_GO <= 1;
78 mSetup_ST <= 1;
79 end
80 1: begin
81 if(mI2C_END)
82 begin
83 if(!mI2C_ACK)
84 mSetup_ST <= 2;
85 else
86 mSetup_ST <= 0;
87 mI2C_GO <= 0;
88 end
89 end
90 2: begin
91 LUT_INDEX <= LUT_INDEX+1;
92 mSetup_ST <= 0;
93 end
94 endcase
95 end
96 end
97 end
98 ////////////////////////////////////////////////////////////////////
99 ///////////////////// Config Data LUT //////////////////////////
100 always
101 begin
102 case(LUT_INDEX)
103 0 : LUT_DATA <= 16'h0000;
104 1 : LUT_DATA <= 16'h2000;
105 2 : LUT_DATA <= 16'hF103; // Mirror Row and Columns
106 3 : LUT_DATA <= {8'h09,iExposure[15:8]};// Exposure
107 4 : LUT_DATA <= {8'hF1,iExposure[7:0]};
108 5 : LUT_DATA <= 16'h2B00; // Green 1 Gain
109 6 : LUT_DATA <= 16'hF1B0;
110 7 : LUT_DATA <= 16'h2C00; // Blue Gain
111 8 : LUT_DATA <= 16'hF1CF;
112 9 : LUT_DATA <= 16'h2D00; // Red Gain
113 10 : LUT_DATA <= 16'hF1CF;
114 11 : LUT_DATA <= 16'h2E00; // Green 2 Gain
115 12 : LUT_DATA <= 16'hF1B0;
116 13 : LUT_DATA <= 16'h0500; // H_Blanking
117 14 : LUT_DATA <= 16'hF188;
118 15 : LUT_DATA <= 16'h0600; // V_Blanking
119 16 : LUT_DATA <= 16'hF119;
120 default:LUT_DATA <= 16'h0000;
121 endcase
122 end
123 ////////////////////////////////////////////////////////////////////
124 endmodule
105行
2 : LUT_DATA <= 16'hF103; // Mirror Row and Columns
原來是16'hF101，改成16'F103後就可以左右正常。
Method 2
在DE2_CCD中，影像其實原本也是左右相反的，但他透過了Mirror_Col將左右影像再做一次mirror變正常，所以我們試著也將DE2_CCD_detect模仿DE2_CCD所使用的技巧。
Step 1：
將DE2_CCD中的Mirror_Col.v與Stack_RAM.v複製到DE2_CCD_detect目錄下。
Step 2：
修改DE2_CCD_detect.v如下
1 // --------------------------------------------------------------------
2 // Copyright (c) 2005 by Terasic Technologies Inc.
3 // --------------------------------------------------------------------
4 //
5 // Permission:
6 //
7 // Terasic grants permission to use and modify this code for use
8 // in synthesis for all Terasic Development Boards and Altera Development
9 // Kits made by Terasic. Other use of this code, including the selling
10 // ,duplication, or modification of any portion is strictly prohibited.
11 //
12 // Disclaimer:
13 //
14 // This VHDL/Verilog or C/C++ source code is intended as a design reference
15 // which illustrates how these types of functions can be implemented.
16 // It is the user's responsibility to verify their design for
17 // consistency and functionality through the use of formal
18 // verification methods. Terasic provides no warranty regarding the use
19 // or functionality of this code.
20 //
21 // --------------------------------------------------------------------
22 //
23 // Terasic Technologies Inc
24 // 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
25 // HsinChu County, Taiwan
26 // 302
27 //
28 // web: http://www.terasic.com/
29 // email: support@terasic.com
30 //
31 // --------------------------------------------------------------------
32 //
33 // Major Functions: DE2 CMOS Camera Demo - Motion Detect
34 //
35 // --------------------------------------------------------------------
36 //
37 // Revision History :
38 // --------------------------------------------------------------------
39 // Ver :| Author :| Mod. Date :| Changes Made:
40 // V1.0 :| Johnny Chen :| 06/02/23 :| Initial Revision
41 // V1.1 :| Johnny Chen :| 06/03/22 :| Change Pin Assignment For New Sensor
42 // V1.2 :| Johnny Chen :| 06/03/22 :| Fixed to Compatible with Quartus II 6.0
43 // --------------------------------------------------------------------
44
45 module DE2_CCD_detect
46 (
47 //////////////////// Clock Input ////////////////////
48 CLOCK_27, // 27 MHz
49 CLOCK_50, // 50 MHz
50 EXT_CLOCK, // External Clock
51 //////////////////// Push Button ////////////////////
52 KEY, // Pushbutton[3:0]
53 //////////////////// DPDT Switch ////////////////////
54 SW, // Toggle Switch[17:0]
55 //////////////////// 7-SEG Dispaly ////////////////////
56 HEX0, // Seven Segment Digit 0
57 HEX1, // Seven Segment Digit 1
58 HEX2, // Seven Segment Digit 2
59 HEX3, // Seven Segment Digit 3
60 HEX4, // Seven Segment Digit 4
61 HEX5, // Seven Segment Digit 5
62 HEX6, // Seven Segment Digit 6
63 HEX7, // Seven Segment Digit 7
64 //////////////////////// LED ////////////////////////
65 LEDG, // LED Green[8:0]
66 LEDR, // LED Red[17:0]
67 //////////////////////// UART ////////////////////////
68 UART_TXD, // UART Transmitter
69 UART_RXD, // UART Receiver
70 //////////////////////// IRDA ////////////////////////
71 IRDA_TXD, // IRDA Transmitter
72 IRDA_RXD, // IRDA Receiver
73 ///////////////////// SDRAM Interface ////////////////
74 DRAM_DQ, // SDRAM Data bus 16 Bits
75 DRAM_ADDR, // SDRAM Address bus 12 Bits
76 DRAM_LDQM, // SDRAM Low-byte Data Mask
77 DRAM_UDQM, // SDRAM High-byte Data Mask
78 DRAM_WE_N, // SDRAM Write Enable
79 DRAM_CAS_N, // SDRAM Column Address Strobe
80 DRAM_RAS_N, // SDRAM Row Address Strobe
81 DRAM_CS_N, // SDRAM Chip Select
82 DRAM_BA_0, // SDRAM Bank Address 0
83 DRAM_BA_1, // SDRAM Bank Address 0
84 DRAM_CLK, // SDRAM Clock
85 DRAM_CKE, // SDRAM Clock Enable
86 //////////////////// Flash Interface ////////////////
87 FL_DQ, // FLASH Data bus 8 Bits
88 FL_ADDR, // FLASH Address bus 22 Bits
89 FL_WE_N, // FLASH Write Enable
90 FL_RST_N, // FLASH Reset
91 FL_OE_N, // FLASH Output Enable
92 FL_CE_N, // FLASH Chip Enable
93 //////////////////// SRAM Interface ////////////////
94 SRAM_DQ, // SRAM Data bus 16 Bits
95 SRAM_ADDR, // SRAM Address bus 18 Bits
96 SRAM_UB_N, // SRAM High-byte Data Mask
97 SRAM_LB_N, // SRAM Low-byte Data Mask
98 SRAM_WE_N, // SRAM Write Enable
99 SRAM_CE_N, // SRAM Chip Enable
100 SRAM_OE_N, // SRAM Output Enable
101 //////////////////// ISP1362 Interface ////////////////
102 OTG_DATA, // ISP1362 Data bus 16 Bits
103 OTG_ADDR, // ISP1362 Address 2 Bits
104 OTG_CS_N, // ISP1362 Chip Select
105 OTG_RD_N, // ISP1362 Write
106 OTG_WR_N, // ISP1362 Read
107 OTG_RST_N, // ISP1362 Reset
108 OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
109 OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
110 OTG_INT0, // ISP1362 Interrupt 0
111 OTG_INT1, // ISP1362 Interrupt 1
112 OTG_DREQ0, // ISP1362 DMA Request 0
113 OTG_DREQ1, // ISP1362 DMA Request 1
114 OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
115 OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
116 //////////////////// LCD Module 16X2 ////////////////
117 LCD_ON, // LCD Power ON/OFF
118 LCD_BLON, // LCD Back Light ON/OFF
119 LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
120 LCD_EN, // LCD Enable
121 LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
122 LCD_DATA, // LCD Data bus 8 bits
123 //////////////////// SD_Card Interface ////////////////
124 SD_DAT, // SD Card Data
125 SD_DAT3, // SD Card Data 3
126 SD_CMD, // SD Card Command Signal
127 SD_CLK, // SD Card Clock
128 //////////////////// USB JTAG link ////////////////////
129 TDI, // CPLD -> FPGA (data in)
130 TCK, // CPLD -> FPGA (clk)
131 TCS, // CPLD -> FPGA (CS)
132 TDO, // FPGA -> CPLD (data out)
133 //////////////////// I2C ////////////////////////////
134 I2C_SDAT, // I2C Data
135 I2C_SCLK, // I2C Clock
136 //////////////////// PS2 ////////////////////////////
137 PS2_DAT, // PS2 Data
138 PS2_CLK, // PS2 Clock
139 //////////////////// VGA ////////////////////////////
140 VGA_CLK, // VGA Clock
141 VGA_HS, // VGA H_SYNC
142 VGA_VS, // VGA V_SYNC
143 VGA_BLANK, // VGA BLANK
144 VGA_SYNC, // VGA SYNC
145 VGA_R, // VGA Red[9:0]
146 VGA_G, // VGA Green[9:0]
147 VGA_B, // VGA Blue[9:0]
148 //////////// Ethernet Interface ////////////////////////
149 ENET_DATA, // DM9000A DATA bus 16Bits
150 ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
151 ENET_CS_N, // DM9000A Chip Select
152 ENET_WR_N, // DM9000A Write
153 ENET_RD_N, // DM9000A Read
154 ENET_RST_N, // DM9000A Reset
155 ENET_INT, // DM9000A Interrupt
156 ENET_CLK, // DM9000A Clock 25 MHz
157 //////////////// Audio CODEC ////////////////////////
158 AUD_ADCLRCK, // Audio CODEC ADC LR Clock
159 AUD_ADCDAT, // Audio CODEC ADC Data
160 AUD_DACLRCK, // Audio CODEC DAC LR Clock
161 AUD_DACDAT, // Audio CODEC DAC Data
162 AUD_BCLK, // Audio CODEC Bit-Stream Clock
163 AUD_XCK, // Audio CODEC Chip Clock
164 //////////////// TV Decoder ////////////////////////
165 TD_DATA, // TV Decoder Data bus 8 bits
166 TD_HS, // TV Decoder H_SYNC
167 TD_VS, // TV Decoder V_SYNC
168 TD_RESET, // TV Decoder Reset
169 //////////////////// GPIO ////////////////////////////
170 GPIO_0, // GPIO Connection 0
171 GPIO_1 // GPIO Connection 1
172 );
173
174 //////////////////////// Clock Input ////////////////////////
175 input CLOCK_27; // 27 MHz
176 input CLOCK_50; // 50 MHz
177 input EXT_CLOCK; // External Clock
178 //////////////////////// Push Button ////////////////////////
179 input [3:0] KEY; // Pushbutton[3:0]
180 //////////////////////// DPDT Switch ////////////////////////
181 input [17:0] SW; // Toggle Switch[17:0]
182 //////////////////////// 7-SEG Dispaly ////////////////////////
183 output [6:0] HEX0; // Seven Segment Digit 0
184 output [6:0] HEX1; // Seven Segment Digit 1
185 output [6:0] HEX2; // Seven Segment Digit 2
186 output [6:0] HEX3; // Seven Segment Digit 3
187 output [6:0] HEX4; // Seven Segment Digit 4
188 output [6:0] HEX5; // Seven Segment Digit 5
189 output [6:0] HEX6; // Seven Segment Digit 6
190 output [6:0] HEX7; // Seven Segment Digit 7
191 //////////////////////////// LED ////////////////////////////
192 output [8:0] LEDG; // LED Green[8:0]
193 output [17:0] LEDR; // LED Red[17:0]
194 //////////////////////////// UART ////////////////////////////
195 output UART_TXD; // UART Transmitter
196 input UART_RXD; // UART Receiver
197 //////////////////////////// IRDA ////////////////////////////
198 output IRDA_TXD; // IRDA Transmitter
199 input IRDA_RXD; // IRDA Receiver
200 /////////////////////// SDRAM Interface ////////////////////////
201 inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
202 output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
203 output DRAM_LDQM; // SDRAM Low-byte Data Mask
204 output DRAM_UDQM; // SDRAM High-byte Data Mask
205 output DRAM_WE_N; // SDRAM Write Enable
206 output DRAM_CAS_N; // SDRAM Column Address Strobe
207 output DRAM_RAS_N; // SDRAM Row Address Strobe
208 output DRAM_CS_N; // SDRAM Chip Select
209 output DRAM_BA_0; // SDRAM Bank Address 0
210 output DRAM_BA_1; // SDRAM Bank Address 0
211 output DRAM_CLK; // SDRAM Clock
212 output DRAM_CKE; // SDRAM Clock Enable
213 //////////////////////// Flash Interface ////////////////////////
214 inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
215 output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
216 output FL_WE_N; // FLASH Write Enable
217 output FL_RST_N; // FLASH Reset
218 output FL_OE_N; // FLASH Output Enable
219 output FL_CE_N; // FLASH Chip Enable
220 //////////////////////// SRAM Interface ////////////////////////
221 inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
222 output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
223 output SRAM_UB_N; // SRAM High-byte Data Mask
224 output SRAM_LB_N; // SRAM Low-byte Data Mask
225 output SRAM_WE_N; // SRAM Write Enable
226 output SRAM_CE_N; // SRAM Chip Enable
227 output SRAM_OE_N; // SRAM Output Enable
228 //////////////////// ISP1362 Interface ////////////////////////
229 inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits
230 output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits
231 output OTG_CS_N; // ISP1362 Chip Select
232 output OTG_RD_N; // ISP1362 Write
233 output OTG_WR_N; // ISP1362 Read
234 output OTG_RST_N; // ISP1362 Reset
235 output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
236 output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
237 input OTG_INT0; // ISP1362 Interrupt 0
238 input OTG_INT1; // ISP1362 Interrupt 1
239 input OTG_DREQ0; // ISP1362 DMA Request 0
240 input OTG_DREQ1; // ISP1362 DMA Request 1
241 output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
242 output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
243 //////////////////// LCD Module 16X2 ////////////////////////////
244 inout [7:0] LCD_DATA; // LCD Data bus 8 bits
245 output LCD_ON; // LCD Power ON/OFF
246 output LCD_BLON; // LCD Back Light ON/OFF
247 output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
248 output LCD_EN; // LCD Enable
249 output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
250 //////////////////// SD Card Interface ////////////////////////
251 inout SD_DAT; // SD Card Data
252 inout SD_DAT3; // SD Card Data 3
253 inout SD_CMD; // SD Card Command Signal
254 output SD_CLK; // SD Card Clock
255 //////////////////////// I2C ////////////////////////////////
256 inout I2C_SDAT; // I2C Data
257 output I2C_SCLK; // I2C Clock
258 //////////////////////// PS2 ////////////////////////////////
259 input PS2_DAT; // PS2 Data
260 input PS2_CLK; // PS2 Clock
261 //////////////////// USB JTAG link ////////////////////////////
262 input TDI; // CPLD -> FPGA (data in)
263 input TCK; // CPLD -> FPGA (clk)
264 input TCS; // CPLD -> FPGA (CS)
265 output TDO; // FPGA -> CPLD (data out)
266 //////////////////////// VGA ////////////////////////////
267 output VGA_CLK; // VGA Clock
268 output VGA_HS; // VGA H_SYNC
269 output VGA_VS; // VGA V_SYNC
270 output VGA_BLANK; // VGA BLANK
271 output VGA_SYNC; // VGA SYNC
272 output [9:0] VGA_R; // VGA Red[9:0]
273 output [9:0] VGA_G; // VGA Green[9:0]
274 output [9:0] VGA_B; // VGA Blue[9:0]
275 //////////////// Ethernet Interface ////////////////////////////
276 inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
277 output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
278 output ENET_CS_N; // DM9000A Chip Select
279 output ENET_WR_N; // DM9000A Write
280 output ENET_RD_N; // DM9000A Read
281 output ENET_RST_N; // DM9000A Reset
282 input ENET_INT; // DM9000A Interrupt
283 output ENET_CLK; // DM9000A Clock 25 MHz
284 //////////////////// Audio CODEC ////////////////////////////
285 inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
286 input AUD_ADCDAT; // Audio CODEC ADC Data
287 inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
288 output AUD_DACDAT; // Audio CODEC DAC Data
289 inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
290 output AUD_XCK; // Audio CODEC Chip Clock
291 //////////////////// TV Devoder ////////////////////////////
292 input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
293 input TD_HS; // TV Decoder H_SYNC
294 input TD_VS; // TV Decoder V_SYNC
295 output TD_RESET; // TV Decoder Reset
296 //////////////////////// GPIO ////////////////////////////////
297 inout [35:0] GPIO_0; // GPIO Connection 0
298 inout [35:0] GPIO_1; // GPIO Connection 1
299
300 assign LCD_ON = 1'b1;
301 assign LCD_BLON = 1'b1;
302 assign TD_RESET = 1'b1;
303 assign AUD_XCK = AUD_CTRL_CLK;
304
305 // All inout port turn to tri-state
306 assign FL_DQ = 8'hzz;
307 assign SRAM_DQ = 16'hzzzz;
308 assign OTG_DATA = 16'hzzzz;
309 assign LCD_DATA = 8'hzz;
310 assign SD_DAT = 1'bz;
311 assign ENET_DATA = 16'hzzzz;
312
313 // CCD
314 wire [9:0] CCD_DATA;
315 wire CCD_SDAT;
316 wire CCD_SCLK;
317 wire CCD_FLASH;
318 wire CCD_FVAL;
319 wire CCD_LVAL;
320 wire CCD_PIXCLK;
321 reg CCD_MCLK; // CCD Master Clock
322
323 wire [15:0] Read_DATA1;
324 wire [15:0] Read_DATA2;
325 wire VGA_CTRL_CLK;
326 wire AUD_CTRL_CLK;
327 wire [9:0] mCCD_DATA;
328 wire mCCD_DVAL;
329 wire mCCD_DVAL_d;
330 wire [10:0] X_Cont;
331 wire [10:0] Y_Cont;
332 wire [9:0] X_ADDR;
333 wire [31:0] Frame_Cont;
334 wire [9:0] mCCD_R;
335 wire [9:0] mCCD_G;
336 wire [9:0] mCCD_B;
337 wire DLY_RST_0;
338 wire DLY_RST_1;
339 wire DLY_RST_2;
340 wire Read;
341 reg [9:0] rCCD_DATA;
342 reg rCCD_LVAL;
343 reg rCCD_FVAL;
344
345 // For Sensor 1
346 assign CCD_DATA[0] = GPIO_1[0];
347 assign CCD_DATA[1] = GPIO_1[1];
348 assign CCD_DATA[2] = GPIO_1[5];
349 assign CCD_DATA[3] = GPIO_1[3];
350 assign CCD_DATA[4] = GPIO_1[2];
351 assign CCD_DATA[5] = GPIO_1[4];
352 assign CCD_DATA[6] = GPIO_1[6];
353 assign CCD_DATA[7] = GPIO_1[7];
354 assign CCD_DATA[8] = GPIO_1[8];
355 assign CCD_DATA[9] = GPIO_1[9];
356 assign GPIO_1[11] = CCD_MCLK;
357 //assign GPIO_1[15] = CCD_SDAT;
358 //assign GPIO_1[14] = CCD_SCLK;
359 assign CCD_FVAL = GPIO_1[13];
360 assign CCD_LVAL = GPIO_1[12];
361 assign CCD_PIXCLK = GPIO_1[10];
362 // For Sensor 2
363 /*
364 assign CCD_DATA[0] = GPIO_1[0+20];
365 assign CCD_DATA[1] = GPIO_1[1+20];
366 assign CCD_DATA[2] = GPIO_1[5+20];
367 assign CCD_DATA[3] = GPIO_1[3+20];
368 assign CCD_DATA[4] = GPIO_1[2+20];
369 assign CCD_DATA[5] = GPIO_1[4+20];
370 assign CCD_DATA[6] = GPIO_1[6+20];
371 assign CCD_DATA[7] = GPIO_1[7+20];
372 assign CCD_DATA[8] = GPIO_1[8+20];
373 assign CCD_DATA[9] = GPIO_1[9+20];
374 assign GPIO_1[11+20] = CCD_MCLK;
375 assign GPIO_1[15+20] = CCD_SDAT;
376 assign GPIO_1[14+20] = CCD_SCLK;
377 assign CCD_FVAL = GPIO_1[13+20];
378 assign CCD_LVAL = GPIO_1[12+20];
379 assign CCD_PIXCLK = GPIO_1[10+20];
380 */
381 assign LEDR = SW;
382 assign LEDG = Y_Cont;
383 assign VGA_CTRL_CLK= CCD_MCLK;
384 assign VGA_CLK = ~CCD_MCLK;
385
386 always@(posedge CLOCK_50) CCD_MCLK <= ~CCD_MCLK;
387
388 always@(posedge CCD_PIXCLK)
389 begin
390 rCCD_DATA <= CCD_DATA;
391 rCCD_LVAL <= CCD_LVAL;
392 rCCD_FVAL <= CCD_FVAL;
393 end
394
395 VGA_Controller u1 ( // Host Side
396 .oRequest(Read),
397 .iRed(mVGA_R),
398 .iGreen(mVGA_G),
399 .iBlue(mVGA_B),
400 .oCoord_X(mVGA_X),
401 .oCoord_Y(mVGA_Y),
402 // VGA Side
403 .oVGA_R(VGA_R),
404 .oVGA_G(VGA_G),
405 .oVGA_B(VGA_B),
406 .oVGA_H_SYNC(VGA_HS),
407 .oVGA_V_SYNC(VGA_VS),
408 .oVGA_SYNC(VGA_SYNC),
409 .oVGA_BLANK(VGA_BLANK),
410 // Control Signal
411 .iCLK(VGA_CTRL_CLK),
412 .iRST_N(DLY_RST_2) );
413
414 Reset_Delay u2 ( .iCLK(CLOCK_50),
415 .iRST(KEY[0]),
416 .oRST_0(DLY_RST_0),
417 .oRST_1(DLY_RST_1),
418 .oRST_2(DLY_RST_2) );
419
420 CCD_Capture u3 ( .oDATA(mCCD_DATA),
421 .oDVAL(mCCD_DVAL),
422 .oX_Cont(X_Cont),
423 .oY_Cont(Y_Cont),
424 .oFrame_Cont(Frame_Cont),
425 .iDATA(rCCD_DATA),
426 .iFVAL(rCCD_FVAL),
427 .iLVAL(rCCD_LVAL),
428 .iSTART(!KEY[3]),
429 .iEND(!KEY[2]),
430 .iCLK(CCD_PIXCLK),
431 .iRST(DLY_RST_1) );
432
433 RAW2RGB u4 ( .oRed(mCCD_R),
434 .oGreen(mCCD_G),
435 .oBlue(mCCD_B),
436 .oDVAL(mCCD_DVAL_d),
437 .iX_Cont(X_Cont),
438 .iY_Cont(Y_Cont),
439 .iDATA(mCCD_DATA),
440 .iDVAL(mCCD_DVAL),
441 .iCLK(CCD_PIXCLK),
442 .iRST(DLY_RST_1) );
443
444 SEG7_LUT_8 u5 ( .oSEG0(HEX0),.oSEG1(HEX1),
445 .oSEG2(HEX2),.oSEG3(HEX3),
446 .oSEG4(HEX4),.oSEG5(HEX5),
447 .oSEG6(HEX6),.oSEG7(HEX7),
448 .iDIG(Frame_Cont) );
449
450 Sdram_Control_4Port u6 (
451 // HOST Side
452 .REF_CLK(CLOCK_50),
453 .RESET_N(1'b1),
454 // FIFO Write Side 1
455 .WR1_DATA({sCCD_R[9:5], sCCD_G[9:5], sCCD_B[9:5]}),
456 .WR1(mCCD_DVAL_d),
457 .WR1_ADDR(0),
458 .WR1_MAX_ADDR(640*512*2),
459 .WR1_LENGTH(9'h100),
460 .WR1_LOAD(!DLY_RST_0),
461 .WR1_CLK(CCD_PIXCLK),
462 // FIFO Read Side 1
463 .RD1_DATA(Read_DATA1),
464 .RD1(Read),
465 .RD1_ADDR(640*16),
466 .RD1_MAX_ADDR(640*496),
467 .RD1_LENGTH(9'h100),
468 .RD1_LOAD(!DLY_RST_0),
469 .RD1_CLK(VGA_CTRL_CLK),
470 // FIFO Read Side 2
471 .RD2_DATA(Read_DATA2),
472 .RD2(Read),
473 .RD2_ADDR(640*512+640*16),
474 .RD2_MAX_ADDR(640*512+640*496),
475 .RD2_LENGTH(9'h100),
476 .RD2_LOAD(!DLY_RST_0),
477 .RD2_CLK(VGA_CTRL_CLK),
478 // SDRAM Side
479 .SA(DRAM_ADDR),
480 .BA({DRAM_BA_1,DRAM_BA_0}),
481 .CS_N(DRAM_CS_N),
482 .CKE(DRAM_CKE),
483 .RAS_N(DRAM_RAS_N),
484 .CAS_N(DRAM_CAS_N),
485 .WE_N(DRAM_WE_N),
486 .DQ(DRAM_DQ),
487 .DQM({DRAM_UDQM,DRAM_LDQM}),
488 .SDR_CLK(DRAM_CLK)
489 );
490
491 I2C_CCD_Config u7 ( // Host Side
492 .iCLK(CLOCK_50),
493 .iRST_N(KEY[1]),
494 .iExposure(SW[15:0]),
495 // I2C Side
496 .I2C_SCLK(GPIO_1[14]),
497 .I2C_SDAT(GPIO_1[15]) );
498
499 I2C_AV_Config u8 ( // Host Side
500 .iCLK(CLOCK_50),
501 .iRST_N(KEY[0]),
502 // I2C Side
503 .I2C_SCLK(I2C_SCLK),
504 .I2C_SDAT(I2C_SDAT) );
505
506 AUDIO_DAC u9 ( // Audio Side
507 .oAUD_BCK(AUD_BCLK),
508 .oAUD_DATA(AUD_DACDAT),
509 .oAUD_LRCK(AUD_DACLRCK),
510 // Control Signals
511 .iSrc_Select(~(SP_cont[21]&SP)),
512 .iCLK_18_4(AUD_CTRL_CLK),
513 .iRST_N(DLY_RST_1) );
514
515 Audio_PLL u10 ( .inclk0(CLOCK_27),.c0(AUD_CTRL_CLK) );
516
517 //====================== motion detect ======================//
518 wire [10:0] mTap_0;
519 reg [10:0] mTap_1,mTap_2,mTap_3,
520 mTap_4,mTap_5,mTap_6,
521 mTap_7,mTap_8,mTap_9,mTap_10;
522 wire [10:0] rTap_0;
523 reg [10:0] rTap_1,rTap_2,rTap_3,
524 rTap_4,rTap_5,rTap_6,
525 rTap_7,rTap_8,rTap_9,rTap_10;
526 wire [10:0] sTap_0;
527 reg [10:0] sTap_1,sTap_2,sTap_3,
528 sTap_4,sTap_5,sTap_6,
529 sTap_7,sTap_8,sTap_9,sTap_10;
530 reg X,Y,Z;
531 reg F1,F2;
532 reg [5:0] Read_d;
533
534 always@(posedge VGA_CTRL_CLK)
535 begin
536 //--------------- binary -------------------//
537 F1 <= ( Read_DATA1[14:10] + Read_DATA1[9:5] + Read_DATA1[4:0] ) >48;
538 F2 <= ( Read_DATA2[14:10] + Read_DATA2[9:5] + Read_DATA2[4:0] ) >48;
539 //---------------------------------------------//
540 mTap_1 <= mTap_0;
541 mTap_2 <= mTap_1;
542 mTap_3 <= mTap_2;
543 mTap_4 <= mTap_3;
544 mTap_5 <= mTap_4;
545 mTap_6 <= mTap_5;
546 mTap_7 <= mTap_6;
547 mTap_8 <= mTap_7;
548 mTap_9 <= mTap_8;
549 mTap_10 <= mTap_9;
550 //--------------- erode -------------------//
551 X <= (&mTap_0) & (&mTap_1) & (&mTap_2) &
552 (&mTap_3) & (&mTap_4) & (&mTap_5) &
553 (&mTap_6) & (&mTap_7) & (&mTap_8) &
554 (&mTap_9) & (&mTap_10);
555 //---------------------------------------------//
556 rTap_1 <= rTap_0;
557 rTap_2 <= rTap_1;
558 rTap_3 <= rTap_2;
559 rTap_4 <= rTap_3;
560 rTap_5 <= rTap_4;
561 rTap_6 <= rTap_5;
562 rTap_7 <= rTap_6;
563 rTap_8 <= rTap_7;
564 rTap_9 <= rTap_8;
565 rTap_10 <= rTap_9;
566 //--------------- dilate -------------------//
567 Y <= (|rTap_0) | (|rTap_1) | (|rTap_2) |
568 (|rTap_3) | (|rTap_4) | (|rTap_5) |
569 (|rTap_6) | (|rTap_7) | (|rTap_8) |
570 (|rTap_9) | (|rTap_10);
571 //---------------------------------------------//
572 sTap_1 <= sTap_0;
573 sTap_2 <= sTap_1;
574 sTap_3 <= sTap_2;
575 sTap_4 <= sTap_3;
576 sTap_5 <= sTap_4;
577 sTap_6 <= sTap_5;
578 sTap_7 <= sTap_6;
579 sTap_8 <= sTap_7;
580 sTap_9 <= sTap_8;
581 sTap_10 <= sTap_9;
582 //--------------- erode -------------------//
583 Z <= (&sTap_0) & (&sTap_1) & (&sTap_2) &
584 (&sTap_3) & (&sTap_4) & (&sTap_5) &
585 (&sTap_6) & (&sTap_7) & (&sTap_8) &
586 (&sTap_9) & (&sTap_10);
587 //---------------------------------------------//
588 Read_d <= {Read_d[4:0],Read};
589 end
590 //--------------- detect method 1 -------------------//
591 Tap_1 u99 ( .clken(Read),
592 .clock(VGA_CTRL_CLK),
593 .shiftin( (Read_DATA1[14:10] ^ Read_DATA2[14:10]) |
594 (Read_DATA1[9:5] ^ Read_DATA2[9:5]) |
595 (Read_DATA1[4:0] ^ Read_DATA2[4:0]) ),
596 .taps(mTap_0));
597
598 Tap_1 u98 ( .clken(Read_d[5]),
599 .clock(VGA_CTRL_CLK),
600 .shiftin(X),
601 .taps(rTap_0));
602 //--------------- detect method 2 -------------------//
603 Tap_1 u97 ( .clken(Read_d[0]),
604 .clock(VGA_CTRL_CLK),
605 .shiftin(F1^F2),
606 .taps(sTap_0));
607 //==================================================================//
608 wire [9:0] mVGA_R = ( (mVGA_X>=20 && mVGA_X<620) && (mVGA_Y>=20 && mVGA_Y<460) )?
609 ( Y|Z ? 1023 : {Read_DATA1[14:10],5'h00} ):
610 {Read_DATA1[14:10],5'h00} ;
611 wire [9:0] mVGA_G = {Read_DATA1[9:5],5'h00};
612 wire [9:0] mVGA_B = {Read_DATA1[4:0],5'h00};
613 wire [9:0] mVGA_X;
614 wire [9:0] mVGA_Y;
615
616 //====================== Speaker Control ====================//
617 reg SP;
618 reg [21:0] SP_cont;
619 reg [23:0] DLY_cont;
620
621 always@(posedge CLOCK_50)
622 begin
623 SP_cont <= SP_cont+1'b1;
624 if(Y|Z) // if datected => turn on speaker
625 DLY_cont <= 0;
626 else
627 begin
628 if(DLY_cont<24'hffffff) // 20 * 2^24 ns
629 begin
630 DLY_cont <= DLY_cont+1;
631 SP <= 1;
632 end
633 else
634 SP <= 0;
635 end
636 end
637 //==================================================================//
638
639 wire [9:0] sCCD_R;
640 wire [9:0] sCCD_G;
641 wire [9:0] sCCD_B;
642 wire sCCD_DVAL;
643
644 Mirror_Col u11 ( // Input Side
645 .iCCD_R(mCCD_R),
646 .iCCD_G(mCCD_G),
647 .iCCD_B(mCCD_B),
648 .iCCD_DVAL(mCCD_DVAL_d),
649 .iCCD_PIXCLK(CCD_PIXCLK),
650 .iRST_N(DLY_RST_1),
651 // Output Side
652 .oCCD_R(sCCD_R),
653 .oCCD_G(sCCD_G),
654 .oCCD_B(sCCD_B),
655 .oCCD_DVAL(sCCD_DVAL)
656 );
657 endmodule
2 // Copyright (c) 2005 by Terasic Technologies Inc.
3 // --------------------------------------------------------------------
4 //
5 // Permission:
6 //
7 // Terasic grants permission to use and modify this code for use
8 // in synthesis for all Terasic Development Boards and Altera Development
9 // Kits made by Terasic. Other use of this code, including the selling
10 // ,duplication, or modification of any portion is strictly prohibited.
11 //
12 // Disclaimer:
13 //
14 // This VHDL/Verilog or C/C++ source code is intended as a design reference
15 // which illustrates how these types of functions can be implemented.
16 // It is the user's responsibility to verify their design for
17 // consistency and functionality through the use of formal
18 // verification methods. Terasic provides no warranty regarding the use
19 // or functionality of this code.
20 //
21 // --------------------------------------------------------------------
22 //
23 // Terasic Technologies Inc
24 // 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
25 // HsinChu County, Taiwan
26 // 302
27 //
28 // web: http://www.terasic.com/
29 // email: support@terasic.com
30 //
31 // --------------------------------------------------------------------
32 //
33 // Major Functions: DE2 CMOS Camera Demo - Motion Detect
34 //
35 // --------------------------------------------------------------------
36 //
37 // Revision History :
38 // --------------------------------------------------------------------
39 // Ver :| Author :| Mod. Date :| Changes Made:
40 // V1.0 :| Johnny Chen :| 06/02/23 :| Initial Revision
41 // V1.1 :| Johnny Chen :| 06/03/22 :| Change Pin Assignment For New Sensor
42 // V1.2 :| Johnny Chen :| 06/03/22 :| Fixed to Compatible with Quartus II 6.0
43 // --------------------------------------------------------------------
44
45 module DE2_CCD_detect
46 (
47 //////////////////// Clock Input ////////////////////
48 CLOCK_27, // 27 MHz
49 CLOCK_50, // 50 MHz
50 EXT_CLOCK, // External Clock
51 //////////////////// Push Button ////////////////////
52 KEY, // Pushbutton[3:0]
53 //////////////////// DPDT Switch ////////////////////
54 SW, // Toggle Switch[17:0]
55 //////////////////// 7-SEG Dispaly ////////////////////
56 HEX0, // Seven Segment Digit 0
57 HEX1, // Seven Segment Digit 1
58 HEX2, // Seven Segment Digit 2
59 HEX3, // Seven Segment Digit 3
60 HEX4, // Seven Segment Digit 4
61 HEX5, // Seven Segment Digit 5
62 HEX6, // Seven Segment Digit 6
63 HEX7, // Seven Segment Digit 7
64 //////////////////////// LED ////////////////////////
65 LEDG, // LED Green[8:0]
66 LEDR, // LED Red[17:0]
67 //////////////////////// UART ////////////////////////
68 UART_TXD, // UART Transmitter
69 UART_RXD, // UART Receiver
70 //////////////////////// IRDA ////////////////////////
71 IRDA_TXD, // IRDA Transmitter
72 IRDA_RXD, // IRDA Receiver
73 ///////////////////// SDRAM Interface ////////////////
74 DRAM_DQ, // SDRAM Data bus 16 Bits
75 DRAM_ADDR, // SDRAM Address bus 12 Bits
76 DRAM_LDQM, // SDRAM Low-byte Data Mask
77 DRAM_UDQM, // SDRAM High-byte Data Mask
78 DRAM_WE_N, // SDRAM Write Enable
79 DRAM_CAS_N, // SDRAM Column Address Strobe
80 DRAM_RAS_N, // SDRAM Row Address Strobe
81 DRAM_CS_N, // SDRAM Chip Select
82 DRAM_BA_0, // SDRAM Bank Address 0
83 DRAM_BA_1, // SDRAM Bank Address 0
84 DRAM_CLK, // SDRAM Clock
85 DRAM_CKE, // SDRAM Clock Enable
86 //////////////////// Flash Interface ////////////////
87 FL_DQ, // FLASH Data bus 8 Bits
88 FL_ADDR, // FLASH Address bus 22 Bits
89 FL_WE_N, // FLASH Write Enable
90 FL_RST_N, // FLASH Reset
91 FL_OE_N, // FLASH Output Enable
92 FL_CE_N, // FLASH Chip Enable
93 //////////////////// SRAM Interface ////////////////
94 SRAM_DQ, // SRAM Data bus 16 Bits
95 SRAM_ADDR, // SRAM Address bus 18 Bits
96 SRAM_UB_N, // SRAM High-byte Data Mask
97 SRAM_LB_N, // SRAM Low-byte Data Mask
98 SRAM_WE_N, // SRAM Write Enable
99 SRAM_CE_N, // SRAM Chip Enable
100 SRAM_OE_N, // SRAM Output Enable
101 //////////////////// ISP1362 Interface ////////////////
102 OTG_DATA, // ISP1362 Data bus 16 Bits
103 OTG_ADDR, // ISP1362 Address 2 Bits
104 OTG_CS_N, // ISP1362 Chip Select
105 OTG_RD_N, // ISP1362 Write
106 OTG_WR_N, // ISP1362 Read
107 OTG_RST_N, // ISP1362 Reset
108 OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
109 OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
110 OTG_INT0, // ISP1362 Interrupt 0
111 OTG_INT1, // ISP1362 Interrupt 1
112 OTG_DREQ0, // ISP1362 DMA Request 0
113 OTG_DREQ1, // ISP1362 DMA Request 1
114 OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
115 OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
116 //////////////////// LCD Module 16X2 ////////////////
117 LCD_ON, // LCD Power ON/OFF
118 LCD_BLON, // LCD Back Light ON/OFF
119 LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
120 LCD_EN, // LCD Enable
121 LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
122 LCD_DATA, // LCD Data bus 8 bits
123 //////////////////// SD_Card Interface ////////////////
124 SD_DAT, // SD Card Data
125 SD_DAT3, // SD Card Data 3
126 SD_CMD, // SD Card Command Signal
127 SD_CLK, // SD Card Clock
128 //////////////////// USB JTAG link ////////////////////
129 TDI, // CPLD -> FPGA (data in)
130 TCK, // CPLD -> FPGA (clk)
131 TCS, // CPLD -> FPGA (CS)
132 TDO, // FPGA -> CPLD (data out)
133 //////////////////// I2C ////////////////////////////
134 I2C_SDAT, // I2C Data
135 I2C_SCLK, // I2C Clock
136 //////////////////// PS2 ////////////////////////////
137 PS2_DAT, // PS2 Data
138 PS2_CLK, // PS2 Clock
139 //////////////////// VGA ////////////////////////////
140 VGA_CLK, // VGA Clock
141 VGA_HS, // VGA H_SYNC
142 VGA_VS, // VGA V_SYNC
143 VGA_BLANK, // VGA BLANK
144 VGA_SYNC, // VGA SYNC
145 VGA_R, // VGA Red[9:0]
146 VGA_G, // VGA Green[9:0]
147 VGA_B, // VGA Blue[9:0]
148 //////////// Ethernet Interface ////////////////////////
149 ENET_DATA, // DM9000A DATA bus 16Bits
150 ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
151 ENET_CS_N, // DM9000A Chip Select
152 ENET_WR_N, // DM9000A Write
153 ENET_RD_N, // DM9000A Read
154 ENET_RST_N, // DM9000A Reset
155 ENET_INT, // DM9000A Interrupt
156 ENET_CLK, // DM9000A Clock 25 MHz
157 //////////////// Audio CODEC ////////////////////////
158 AUD_ADCLRCK, // Audio CODEC ADC LR Clock
159 AUD_ADCDAT, // Audio CODEC ADC Data
160 AUD_DACLRCK, // Audio CODEC DAC LR Clock
161 AUD_DACDAT, // Audio CODEC DAC Data
162 AUD_BCLK, // Audio CODEC Bit-Stream Clock
163 AUD_XCK, // Audio CODEC Chip Clock
164 //////////////// TV Decoder ////////////////////////
165 TD_DATA, // TV Decoder Data bus 8 bits
166 TD_HS, // TV Decoder H_SYNC
167 TD_VS, // TV Decoder V_SYNC
168 TD_RESET, // TV Decoder Reset
169 //////////////////// GPIO ////////////////////////////
170 GPIO_0, // GPIO Connection 0
171 GPIO_1 // GPIO Connection 1
172 );
173
174 //////////////////////// Clock Input ////////////////////////
175 input CLOCK_27; // 27 MHz
176 input CLOCK_50; // 50 MHz
177 input EXT_CLOCK; // External Clock
178 //////////////////////// Push Button ////////////////////////
179 input [3:0] KEY; // Pushbutton[3:0]
180 //////////////////////// DPDT Switch ////////////////////////
181 input [17:0] SW; // Toggle Switch[17:0]
182 //////////////////////// 7-SEG Dispaly ////////////////////////
183 output [6:0] HEX0; // Seven Segment Digit 0
184 output [6:0] HEX1; // Seven Segment Digit 1
185 output [6:0] HEX2; // Seven Segment Digit 2
186 output [6:0] HEX3; // Seven Segment Digit 3
187 output [6:0] HEX4; // Seven Segment Digit 4
188 output [6:0] HEX5; // Seven Segment Digit 5
189 output [6:0] HEX6; // Seven Segment Digit 6
190 output [6:0] HEX7; // Seven Segment Digit 7
191 //////////////////////////// LED ////////////////////////////
192 output [8:0] LEDG; // LED Green[8:0]
193 output [17:0] LEDR; // LED Red[17:0]
194 //////////////////////////// UART ////////////////////////////
195 output UART_TXD; // UART Transmitter
196 input UART_RXD; // UART Receiver
197 //////////////////////////// IRDA ////////////////////////////
198 output IRDA_TXD; // IRDA Transmitter
199 input IRDA_RXD; // IRDA Receiver
200 /////////////////////// SDRAM Interface ////////////////////////
201 inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
202 output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
203 output DRAM_LDQM; // SDRAM Low-byte Data Mask
204 output DRAM_UDQM; // SDRAM High-byte Data Mask
205 output DRAM_WE_N; // SDRAM Write Enable
206 output DRAM_CAS_N; // SDRAM Column Address Strobe
207 output DRAM_RAS_N; // SDRAM Row Address Strobe
208 output DRAM_CS_N; // SDRAM Chip Select
209 output DRAM_BA_0; // SDRAM Bank Address 0
210 output DRAM_BA_1; // SDRAM Bank Address 0
211 output DRAM_CLK; // SDRAM Clock
212 output DRAM_CKE; // SDRAM Clock Enable
213 //////////////////////// Flash Interface ////////////////////////
214 inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
215 output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
216 output FL_WE_N; // FLASH Write Enable
217 output FL_RST_N; // FLASH Reset
218 output FL_OE_N; // FLASH Output Enable
219 output FL_CE_N; // FLASH Chip Enable
220 //////////////////////// SRAM Interface ////////////////////////
221 inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
222 output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
223 output SRAM_UB_N; // SRAM High-byte Data Mask
224 output SRAM_LB_N; // SRAM Low-byte Data Mask
225 output SRAM_WE_N; // SRAM Write Enable
226 output SRAM_CE_N; // SRAM Chip Enable
227 output SRAM_OE_N; // SRAM Output Enable
228 //////////////////// ISP1362 Interface ////////////////////////
229 inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits
230 output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits
231 output OTG_CS_N; // ISP1362 Chip Select
232 output OTG_RD_N; // ISP1362 Write
233 output OTG_WR_N; // ISP1362 Read
234 output OTG_RST_N; // ISP1362 Reset
235 output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
236 output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
237 input OTG_INT0; // ISP1362 Interrupt 0
238 input OTG_INT1; // ISP1362 Interrupt 1
239 input OTG_DREQ0; // ISP1362 DMA Request 0
240 input OTG_DREQ1; // ISP1362 DMA Request 1
241 output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
242 output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
243 //////////////////// LCD Module 16X2 ////////////////////////////
244 inout [7:0] LCD_DATA; // LCD Data bus 8 bits
245 output LCD_ON; // LCD Power ON/OFF
246 output LCD_BLON; // LCD Back Light ON/OFF
247 output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
248 output LCD_EN; // LCD Enable
249 output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
250 //////////////////// SD Card Interface ////////////////////////
251 inout SD_DAT; // SD Card Data
252 inout SD_DAT3; // SD Card Data 3
253 inout SD_CMD; // SD Card Command Signal
254 output SD_CLK; // SD Card Clock
255 //////////////////////// I2C ////////////////////////////////
256 inout I2C_SDAT; // I2C Data
257 output I2C_SCLK; // I2C Clock
258 //////////////////////// PS2 ////////////////////////////////
259 input PS2_DAT; // PS2 Data
260 input PS2_CLK; // PS2 Clock
261 //////////////////// USB JTAG link ////////////////////////////
262 input TDI; // CPLD -> FPGA (data in)
263 input TCK; // CPLD -> FPGA (clk)
264 input TCS; // CPLD -> FPGA (CS)
265 output TDO; // FPGA -> CPLD (data out)
266 //////////////////////// VGA ////////////////////////////
267 output VGA_CLK; // VGA Clock
268 output VGA_HS; // VGA H_SYNC
269 output VGA_VS; // VGA V_SYNC
270 output VGA_BLANK; // VGA BLANK
271 output VGA_SYNC; // VGA SYNC
272 output [9:0] VGA_R; // VGA Red[9:0]
273 output [9:0] VGA_G; // VGA Green[9:0]
274 output [9:0] VGA_B; // VGA Blue[9:0]
275 //////////////// Ethernet Interface ////////////////////////////
276 inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
277 output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
278 output ENET_CS_N; // DM9000A Chip Select
279 output ENET_WR_N; // DM9000A Write
280 output ENET_RD_N; // DM9000A Read
281 output ENET_RST_N; // DM9000A Reset
282 input ENET_INT; // DM9000A Interrupt
283 output ENET_CLK; // DM9000A Clock 25 MHz
284 //////////////////// Audio CODEC ////////////////////////////
285 inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
286 input AUD_ADCDAT; // Audio CODEC ADC Data
287 inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
288 output AUD_DACDAT; // Audio CODEC DAC Data
289 inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
290 output AUD_XCK; // Audio CODEC Chip Clock
291 //////////////////// TV Devoder ////////////////////////////
292 input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
293 input TD_HS; // TV Decoder H_SYNC
294 input TD_VS; // TV Decoder V_SYNC
295 output TD_RESET; // TV Decoder Reset
296 //////////////////////// GPIO ////////////////////////////////
297 inout [35:0] GPIO_0; // GPIO Connection 0
298 inout [35:0] GPIO_1; // GPIO Connection 1
299
300 assign LCD_ON = 1'b1;
301 assign LCD_BLON = 1'b1;
302 assign TD_RESET = 1'b1;
303 assign AUD_XCK = AUD_CTRL_CLK;
304
305 // All inout port turn to tri-state
306 assign FL_DQ = 8'hzz;
307 assign SRAM_DQ = 16'hzzzz;
308 assign OTG_DATA = 16'hzzzz;
309 assign LCD_DATA = 8'hzz;
310 assign SD_DAT = 1'bz;
311 assign ENET_DATA = 16'hzzzz;
312
313 // CCD
314 wire [9:0] CCD_DATA;
315 wire CCD_SDAT;
316 wire CCD_SCLK;
317 wire CCD_FLASH;
318 wire CCD_FVAL;
319 wire CCD_LVAL;
320 wire CCD_PIXCLK;
321 reg CCD_MCLK; // CCD Master Clock
322
323 wire [15:0] Read_DATA1;
324 wire [15:0] Read_DATA2;
325 wire VGA_CTRL_CLK;
326 wire AUD_CTRL_CLK;
327 wire [9:0] mCCD_DATA;
328 wire mCCD_DVAL;
329 wire mCCD_DVAL_d;
330 wire [10:0] X_Cont;
331 wire [10:0] Y_Cont;
332 wire [9:0] X_ADDR;
333 wire [31:0] Frame_Cont;
334 wire [9:0] mCCD_R;
335 wire [9:0] mCCD_G;
336 wire [9:0] mCCD_B;
337 wire DLY_RST_0;
338 wire DLY_RST_1;
339 wire DLY_RST_2;
340 wire Read;
341 reg [9:0] rCCD_DATA;
342 reg rCCD_LVAL;
343 reg rCCD_FVAL;
344
345 // For Sensor 1
346 assign CCD_DATA[0] = GPIO_1[0];
347 assign CCD_DATA[1] = GPIO_1[1];
348 assign CCD_DATA[2] = GPIO_1[5];
349 assign CCD_DATA[3] = GPIO_1[3];
350 assign CCD_DATA[4] = GPIO_1[2];
351 assign CCD_DATA[5] = GPIO_1[4];
352 assign CCD_DATA[6] = GPIO_1[6];
353 assign CCD_DATA[7] = GPIO_1[7];
354 assign CCD_DATA[8] = GPIO_1[8];
355 assign CCD_DATA[9] = GPIO_1[9];
356 assign GPIO_1[11] = CCD_MCLK;
357 //assign GPIO_1[15] = CCD_SDAT;
358 //assign GPIO_1[14] = CCD_SCLK;
359 assign CCD_FVAL = GPIO_1[13];
360 assign CCD_LVAL = GPIO_1[12];
361 assign CCD_PIXCLK = GPIO_1[10];
362 // For Sensor 2
363 /*
364 assign CCD_DATA[0] = GPIO_1[0+20];
365 assign CCD_DATA[1] = GPIO_1[1+20];
366 assign CCD_DATA[2] = GPIO_1[5+20];
367 assign CCD_DATA[3] = GPIO_1[3+20];
368 assign CCD_DATA[4] = GPIO_1[2+20];
369 assign CCD_DATA[5] = GPIO_1[4+20];
370 assign CCD_DATA[6] = GPIO_1[6+20];
371 assign CCD_DATA[7] = GPIO_1[7+20];
372 assign CCD_DATA[8] = GPIO_1[8+20];
373 assign CCD_DATA[9] = GPIO_1[9+20];
374 assign GPIO_1[11+20] = CCD_MCLK;
375 assign GPIO_1[15+20] = CCD_SDAT;
376 assign GPIO_1[14+20] = CCD_SCLK;
377 assign CCD_FVAL = GPIO_1[13+20];
378 assign CCD_LVAL = GPIO_1[12+20];
379 assign CCD_PIXCLK = GPIO_1[10+20];
380 */
381 assign LEDR = SW;
382 assign LEDG = Y_Cont;
383 assign VGA_CTRL_CLK= CCD_MCLK;
384 assign VGA_CLK = ~CCD_MCLK;
385
386 always@(posedge CLOCK_50) CCD_MCLK <= ~CCD_MCLK;
387
388 always@(posedge CCD_PIXCLK)
389 begin
390 rCCD_DATA <= CCD_DATA;
391 rCCD_LVAL <= CCD_LVAL;
392 rCCD_FVAL <= CCD_FVAL;
393 end
394
395 VGA_Controller u1 ( // Host Side
396 .oRequest(Read),
397 .iRed(mVGA_R),
398 .iGreen(mVGA_G),
399 .iBlue(mVGA_B),
400 .oCoord_X(mVGA_X),
401 .oCoord_Y(mVGA_Y),
402 // VGA Side
403 .oVGA_R(VGA_R),
404 .oVGA_G(VGA_G),
405 .oVGA_B(VGA_B),
406 .oVGA_H_SYNC(VGA_HS),
407 .oVGA_V_SYNC(VGA_VS),
408 .oVGA_SYNC(VGA_SYNC),
409 .oVGA_BLANK(VGA_BLANK),
410 // Control Signal
411 .iCLK(VGA_CTRL_CLK),
412 .iRST_N(DLY_RST_2) );
413
414 Reset_Delay u2 ( .iCLK(CLOCK_50),
415 .iRST(KEY[0]),
416 .oRST_0(DLY_RST_0),
417 .oRST_1(DLY_RST_1),
418 .oRST_2(DLY_RST_2) );
419
420 CCD_Capture u3 ( .oDATA(mCCD_DATA),
421 .oDVAL(mCCD_DVAL),
422 .oX_Cont(X_Cont),
423 .oY_Cont(Y_Cont),
424 .oFrame_Cont(Frame_Cont),
425 .iDATA(rCCD_DATA),
426 .iFVAL(rCCD_FVAL),
427 .iLVAL(rCCD_LVAL),
428 .iSTART(!KEY[3]),
429 .iEND(!KEY[2]),
430 .iCLK(CCD_PIXCLK),
431 .iRST(DLY_RST_1) );
432
433 RAW2RGB u4 ( .oRed(mCCD_R),
434 .oGreen(mCCD_G),
435 .oBlue(mCCD_B),
436 .oDVAL(mCCD_DVAL_d),
437 .iX_Cont(X_Cont),
438 .iY_Cont(Y_Cont),
439 .iDATA(mCCD_DATA),
440 .iDVAL(mCCD_DVAL),
441 .iCLK(CCD_PIXCLK),
442 .iRST(DLY_RST_1) );
443
444 SEG7_LUT_8 u5 ( .oSEG0(HEX0),.oSEG1(HEX1),
445 .oSEG2(HEX2),.oSEG3(HEX3),
446 .oSEG4(HEX4),.oSEG5(HEX5),
447 .oSEG6(HEX6),.oSEG7(HEX7),
448 .iDIG(Frame_Cont) );
449
450 Sdram_Control_4Port u6 (
451 // HOST Side
452 .REF_CLK(CLOCK_50),
453 .RESET_N(1'b1),
454 // FIFO Write Side 1
455 .WR1_DATA({sCCD_R[9:5], sCCD_G[9:5], sCCD_B[9:5]}),
456 .WR1(mCCD_DVAL_d),
457 .WR1_ADDR(0),
458 .WR1_MAX_ADDR(640*512*2),
459 .WR1_LENGTH(9'h100),
460 .WR1_LOAD(!DLY_RST_0),
461 .WR1_CLK(CCD_PIXCLK),
462 // FIFO Read Side 1
463 .RD1_DATA(Read_DATA1),
464 .RD1(Read),
465 .RD1_ADDR(640*16),
466 .RD1_MAX_ADDR(640*496),
467 .RD1_LENGTH(9'h100),
468 .RD1_LOAD(!DLY_RST_0),
469 .RD1_CLK(VGA_CTRL_CLK),
470 // FIFO Read Side 2
471 .RD2_DATA(Read_DATA2),
472 .RD2(Read),
473 .RD2_ADDR(640*512+640*16),
474 .RD2_MAX_ADDR(640*512+640*496),
475 .RD2_LENGTH(9'h100),
476 .RD2_LOAD(!DLY_RST_0),
477 .RD2_CLK(VGA_CTRL_CLK),
478 // SDRAM Side
479 .SA(DRAM_ADDR),
480 .BA({DRAM_BA_1,DRAM_BA_0}),
481 .CS_N(DRAM_CS_N),
482 .CKE(DRAM_CKE),
483 .RAS_N(DRAM_RAS_N),
484 .CAS_N(DRAM_CAS_N),
485 .WE_N(DRAM_WE_N),
486 .DQ(DRAM_DQ),
487 .DQM({DRAM_UDQM,DRAM_LDQM}),
488 .SDR_CLK(DRAM_CLK)
489 );
490
491 I2C_CCD_Config u7 ( // Host Side
492 .iCLK(CLOCK_50),
493 .iRST_N(KEY[1]),
494 .iExposure(SW[15:0]),
495 // I2C Side
496 .I2C_SCLK(GPIO_1[14]),
497 .I2C_SDAT(GPIO_1[15]) );
498
499 I2C_AV_Config u8 ( // Host Side
500 .iCLK(CLOCK_50),
501 .iRST_N(KEY[0]),
502 // I2C Side
503 .I2C_SCLK(I2C_SCLK),
504 .I2C_SDAT(I2C_SDAT) );
505
506 AUDIO_DAC u9 ( // Audio Side
507 .oAUD_BCK(AUD_BCLK),
508 .oAUD_DATA(AUD_DACDAT),
509 .oAUD_LRCK(AUD_DACLRCK),
510 // Control Signals
511 .iSrc_Select(~(SP_cont[21]&SP)),
512 .iCLK_18_4(AUD_CTRL_CLK),
513 .iRST_N(DLY_RST_1) );
514
515 Audio_PLL u10 ( .inclk0(CLOCK_27),.c0(AUD_CTRL_CLK) );
516
517 //====================== motion detect ======================//
518 wire [10:0] mTap_0;
519 reg [10:0] mTap_1,mTap_2,mTap_3,
520 mTap_4,mTap_5,mTap_6,
521 mTap_7,mTap_8,mTap_9,mTap_10;
522 wire [10:0] rTap_0;
523 reg [10:0] rTap_1,rTap_2,rTap_3,
524 rTap_4,rTap_5,rTap_6,
525 rTap_7,rTap_8,rTap_9,rTap_10;
526 wire [10:0] sTap_0;
527 reg [10:0] sTap_1,sTap_2,sTap_3,
528 sTap_4,sTap_5,sTap_6,
529 sTap_7,sTap_8,sTap_9,sTap_10;
530 reg X,Y,Z;
531 reg F1,F2;
532 reg [5:0] Read_d;
533
534 always@(posedge VGA_CTRL_CLK)
535 begin
536 //--------------- binary -------------------//
537 F1 <= ( Read_DATA1[14:10] + Read_DATA1[9:5] + Read_DATA1[4:0] ) >48;
538 F2 <= ( Read_DATA2[14:10] + Read_DATA2[9:5] + Read_DATA2[4:0] ) >48;
539 //---------------------------------------------//
540 mTap_1 <= mTap_0;
541 mTap_2 <= mTap_1;
542 mTap_3 <= mTap_2;
543 mTap_4 <= mTap_3;
544 mTap_5 <= mTap_4;
545 mTap_6 <= mTap_5;
546 mTap_7 <= mTap_6;
547 mTap_8 <= mTap_7;
548 mTap_9 <= mTap_8;
549 mTap_10 <= mTap_9;
550 //--------------- erode -------------------//
551 X <= (&mTap_0) & (&mTap_1) & (&mTap_2) &
552 (&mTap_3) & (&mTap_4) & (&mTap_5) &
553 (&mTap_6) & (&mTap_7) & (&mTap_8) &
554 (&mTap_9) & (&mTap_10);
555 //---------------------------------------------//
556 rTap_1 <= rTap_0;
557 rTap_2 <= rTap_1;
558 rTap_3 <= rTap_2;
559 rTap_4 <= rTap_3;
560 rTap_5 <= rTap_4;
561 rTap_6 <= rTap_5;
562 rTap_7 <= rTap_6;
563 rTap_8 <= rTap_7;
564 rTap_9 <= rTap_8;
565 rTap_10 <= rTap_9;
566 //--------------- dilate -------------------//
567 Y <= (|rTap_0) | (|rTap_1) | (|rTap_2) |
568 (|rTap_3) | (|rTap_4) | (|rTap_5) |
569 (|rTap_6) | (|rTap_7) | (|rTap_8) |
570 (|rTap_9) | (|rTap_10);
571 //---------------------------------------------//
572 sTap_1 <= sTap_0;
573 sTap_2 <= sTap_1;
574 sTap_3 <= sTap_2;
575 sTap_4 <= sTap_3;
576 sTap_5 <= sTap_4;
577 sTap_6 <= sTap_5;
578 sTap_7 <= sTap_6;
579 sTap_8 <= sTap_7;
580 sTap_9 <= sTap_8;
581 sTap_10 <= sTap_9;
582 //--------------- erode -------------------//
583 Z <= (&sTap_0) & (&sTap_1) & (&sTap_2) &
584 (&sTap_3) & (&sTap_4) & (&sTap_5) &
585 (&sTap_6) & (&sTap_7) & (&sTap_8) &
586 (&sTap_9) & (&sTap_10);
587 //---------------------------------------------//
588 Read_d <= {Read_d[4:0],Read};
589 end
590 //--------------- detect method 1 -------------------//
591 Tap_1 u99 ( .clken(Read),
592 .clock(VGA_CTRL_CLK),
593 .shiftin( (Read_DATA1[14:10] ^ Read_DATA2[14:10]) |
594 (Read_DATA1[9:5] ^ Read_DATA2[9:5]) |
595 (Read_DATA1[4:0] ^ Read_DATA2[4:0]) ),
596 .taps(mTap_0));
597
598 Tap_1 u98 ( .clken(Read_d[5]),
599 .clock(VGA_CTRL_CLK),
600 .shiftin(X),
601 .taps(rTap_0));
602 //--------------- detect method 2 -------------------//
603 Tap_1 u97 ( .clken(Read_d[0]),
604 .clock(VGA_CTRL_CLK),
605 .shiftin(F1^F2),
606 .taps(sTap_0));
607 //==================================================================//
608 wire [9:0] mVGA_R = ( (mVGA_X>=20 && mVGA_X<620) && (mVGA_Y>=20 && mVGA_Y<460) )?
609 ( Y|Z ? 1023 : {Read_DATA1[14:10],5'h00} ):
610 {Read_DATA1[14:10],5'h00} ;
611 wire [9:0] mVGA_G = {Read_DATA1[9:5],5'h00};
612 wire [9:0] mVGA_B = {Read_DATA1[4:0],5'h00};
613 wire [9:0] mVGA_X;
614 wire [9:0] mVGA_Y;
615
616 //====================== Speaker Control ====================//
617 reg SP;
618 reg [21:0] SP_cont;
619 reg [23:0] DLY_cont;
620
621 always@(posedge CLOCK_50)
622 begin
623 SP_cont <= SP_cont+1'b1;
624 if(Y|Z) // if datected => turn on speaker
625 DLY_cont <= 0;
626 else
627 begin
628 if(DLY_cont<24'hffffff) // 20 * 2^24 ns
629 begin
630 DLY_cont <= DLY_cont+1;
631 SP <= 1;
632 end
633 else
634 SP <= 0;
635 end
636 end
637 //==================================================================//
638
639 wire [9:0] sCCD_R;
640 wire [9:0] sCCD_G;
641 wire [9:0] sCCD_B;
642 wire sCCD_DVAL;
643
644 Mirror_Col u11 ( // Input Side
645 .iCCD_R(mCCD_R),
646 .iCCD_G(mCCD_G),
647 .iCCD_B(mCCD_B),
648 .iCCD_DVAL(mCCD_DVAL_d),
649 .iCCD_PIXCLK(CCD_PIXCLK),
650 .iRST_N(DLY_RST_1),
651 // Output Side
652 .oCCD_R(sCCD_R),
653 .oCCD_G(sCCD_G),
654 .oCCD_B(sCCD_B),
655 .oCCD_DVAL(sCCD_DVAL)
656 );
657 endmodule
639行
wire [9:0] sCCD_R;
wire [9:0] sCCD_G;
wire [9:0] sCCD_B;
wire sCCD_DVAL;
Mirror_Col u11 ( // Input Side
.iCCD_R(mCCD_R),
.iCCD_G(mCCD_G),
.iCCD_B(mCCD_B),
.iCCD_DVAL(mCCD_DVAL_d),
.iCCD_PIXCLK(CCD_PIXCLK),
.iRST_N(DLY_RST_1),
// Output Side
.oCCD_R(sCCD_R),
.oCCD_G(sCCD_G),
.oCCD_B(sCCD_B),
.oCCD_DVAL(sCCD_DVAL)
);
wire [9:0] sCCD_G;
wire [9:0] sCCD_B;
wire sCCD_DVAL;
Mirror_Col u11 ( // Input Side
.iCCD_R(mCCD_R),
.iCCD_G(mCCD_G),
.iCCD_B(mCCD_B),
.iCCD_DVAL(mCCD_DVAL_d),
.iCCD_PIXCLK(CCD_PIXCLK),
.iRST_N(DLY_RST_1),
// Output Side
.oCCD_R(sCCD_R),
.oCCD_G(sCCD_G),
.oCCD_B(sCCD_B),
.oCCD_DVAL(sCCD_DVAL)
);
加上以上Mirror_Col，將mCCD_R、mCCD_G、mCCD_B輸入，輸出sCCD_R、sCCD_G、sCCD_B。
450行
Sdram_Control_4Port u6 (
// HOST Side
.REF_CLK(CLOCK_50),
.RESET_N(1'b1),
// FIFO Write Side 1
.WR1_DATA({sCCD_R[9:5], sCCD_G[9:5], sCCD_B[9:5]}),
.WR1(mCCD_DVAL_d),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*512*2),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD_PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(Read),
.RD1_ADDR(640*16),
.RD1_MAX_ADDR(640*496),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(VGA_CTRL_CLK),
// FIFO Read Side 2
.RD2_DATA(Read_DATA2),
.RD2(Read),
.RD2_ADDR(640*512+640*16),
.RD2_MAX_ADDR(640*512+640*496),
.RD2_LENGTH(9'h100),
.RD2_LOAD(!DLY_RST_0),
.RD2_CLK(VGA_CTRL_CLK),
// SDRAM Side
.SA(DRAM_ADDR),
.BA({DRAM_BA_1,DRAM_BA_0}),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK)
);
// HOST Side
.REF_CLK(CLOCK_50),
.RESET_N(1'b1),
// FIFO Write Side 1
.WR1_DATA({sCCD_R[9:5], sCCD_G[9:5], sCCD_B[9:5]}),
.WR1(mCCD_DVAL_d),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*512*2),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD_PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(Read),
.RD1_ADDR(640*16),
.RD1_MAX_ADDR(640*496),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(VGA_CTRL_CLK),
// FIFO Read Side 2
.RD2_DATA(Read_DATA2),
.RD2(Read),
.RD2_ADDR(640*512+640*16),
.RD2_MAX_ADDR(640*512+640*496),
.RD2_LENGTH(9'h100),
.RD2_LOAD(!DLY_RST_0),
.RD2_CLK(VGA_CTRL_CLK),
// SDRAM Side
.SA(DRAM_ADDR),
.BA({DRAM_BA_1,DRAM_BA_0}),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK)
);
將輸出的sCCD_R、sCCD_G、sCCD_B傳入Sdram_Control_4Port。
完整程式碼下載
友晶科技範例 DE2_CCD.7z
友晶科技範例 DE2_CCD_detect.7z
Method 1 DE2_CCD_detect_hinverse_1.7z、DE2_CCD_no_mirror.7z
Method 2 DE2_CCD_detect_hinverse_2.7z
See Also
(原創) 如何將CMOS彩色影像轉換成灰階影像? (SOC) (DE2)
(原創) 如何解決DE2_LCM_CCD上下顛倒左右相反的問題? (SOC) (DE2)
