【实验】简单实时300点采样逻辑
工程文件: /Files/lwpo2008/SampleLogicRealTime.rar
RTL图:
![](https://images.cnblogs.com/cnblogs_com/lwpo2008/SampleLogicRealTime.jpg)
状态转换图:
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module SampleLogicRealTime(
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input rst_n,
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input iclk,
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input trig,
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output oclk
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);
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parameter IDLE = 2'b01,
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SAMPLE = 2'b10;
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parameter LENGTH = 9'd300;
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reg [1:0] current_state, //state
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next_state;
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reg r_data_in0, //detect the risingedge reg
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r_data_in1,
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o_rising_edge;
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reg [8:0] count; //count for delay
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reg count_rst_n;
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// sequential circuit
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always@(posedge iclk, negedge rst_n) begin
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if (!rst_n) begin
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current_state <= IDLE;
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end
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else begin
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current_state <= next_state;
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end
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end
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// combinational circuit for state logic
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always@(current_state,count,o_rising_edge) begin
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next_state = IDLE;
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case (current_state)
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IDLE : next_state = o_rising_edge ? SAMPLE : IDLE;
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SAMPLE : next_state = (count >= LENGTH) ? IDLE : SAMPLE;
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endcase
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end
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assign oclk = (count_rst_n ==1'b0)? 1'b0 : iclk;
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// combinational circuit for output logic
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always@(current_state,iclk) begin
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case (current_state)
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IDLE : begin
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count_rst_n <= 1'b0;
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end
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SAMPLE : begin
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count_rst_n <= 1'b1;
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end
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endcase
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end
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//detect the rising edge
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always@(posedge iclk) begin
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r_data_in0 <= r_data_in1;
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r_data_in1 <= trig;
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end
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always@(r_data_in0,r_data_in1) begin
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o_rising_edge = ~r_data_in0 & r_data_in1; //o_rising_edge output
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end
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//counter
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always@(posedge iclk) begin
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if(~count_rst_n)
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count <= 9'b0_0000_0000;
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else
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count <= count + 1'b1;
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end
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endmodule
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RTL图:
![](https://images.cnblogs.com/cnblogs_com/lwpo2008/SampleLogicRealTime.jpg)
状态转换图:
![](https://images.cnblogs.com/cnblogs_com/lwpo2008/SampleLogicRealTime_State.jpg)
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