s3c2440 移值u-boot-2016.03 第2篇 支持Nand flash启动
1, 要求：在4K 的代码以内，完成 NOR NAND 类型判断，初始化 NAND 复制自身到 SDRAM ，重定向。
2, 在 /arch/arm/cpu/arm920t/ 文件夹里 添加一个 inic.c 的文件，要在这个文件里面做上面说的事情。
修改 /arch/arm/cpu/arm920t/Makefile 加入 inic.c 的 编译。
extra-y = start.o
obj-y += init.o
obj-y += cpu.o
init.c 最后有补丁文件
3, 在 start.S 中初始化 SP 后调用 init.c 中的 初始化 NAND FLASH 和 复制 u-boot 到 SDRAM 清BSS 等
ldr sp, =4096 #在 NOR 启动时定在这里是不能写的，sp 中通常是保存 入栈 出栈 ， 局部变量等，因为函数中并没有用到，设不设这里都可以。
bl init_sdram
ldr sp, =0x34000000
bl nand_init_ll
/**
* 从 0 地址开始复制 到 SDRAM 中
* 在 smdk2440.h 中定义 #define CONFIG_SYS_TEXT_BASE
* u-boot 的加载地址
*/
mov r0,#0
ldr r1,=CONFIG_SYS_TEXT_BASE
ldr r2,=__bss_start
sub r2, r2, r1
bl copy_code_to_sdram
bl clear_bss #清不清都可以，因为重定向那里还要在清一次，为了以后去掉重定向这里也清。
#从片内 4K 跳到 SDRAM 中 bl 不行，要用 ldr pc
ldr pc,=_main
4, 启用流程
/arch/arm/cpu/arm920t/start.S
/arch/arm/lib/crt0.S
u-boot 第一阶段
/common/Board_f.c 中的 board_init_f() 函数
最后调用
jump_to_copy()
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
调用/arch/arm/librelocate.S relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
执行完毕后返回
crt0.S
bl board_init_f
下面直接执行第2阶段，也是因为执行了重定位，bl 跳不了
ldr pc, =board_init_r
5, 如何兼容 NOR FLASH NAND FLASH 启用？
不改动 原来的 重定位代码比较简单。
兼容 NOR FLASH NAND FLASH 的方法是，如果不想修改重定位的代码，就是先把 u-boot 复制到
SDRAM 的一个低地址，然后，它会从 这里在复制到 SDRAM 的高地址去。
NAND FLASH 启用要做的就是，在 4K 自动复制的代码里面，实现把u-boot 复制到 SDRAM 的低地址
6, 确定一个可用的链接地址
crt0.S
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
这里先把 sp 定在了最低端，因此不能使用 0x30000000
又因为u-boot 最终会被放到高地址也不能用 0x34000000
因为内存很大，放在10M 的位置吧。
在 smdk2440.h 中定义 #define CONFIG_SYS_TEXT_BASE 0x30a00000
补丁文件：
1 diff -urN u-boot-2016.03/arch/arm/cpu/arm920t/init.c u-boot-2016.03-ok/arch/arm/cpu/arm920t/init.c 2 --- u-boot-2016.03/arch/arm/cpu/arm920t/init.c 1970-01-01 07:00:00.000000000 +0700 3 +++ u-boot-2016.03-ok/arch/arm/cpu/arm920t/init.c 2016-05-17 06:48:31.635438931 +0800 4 @@ -0,0 +1,196 @@ 5 +/* NAND FLASH控制器 */ 6 +#define NFCONF (*((volatile unsigned long *)0x4E000000)) 7 +#define NFCONT (*((volatile unsigned long *)0x4E000004)) 8 +#define NFCMMD (*((volatile unsigned char *)0x4E000008)) 9 +#define NFADDR (*((volatile unsigned char *)0x4E00000C)) 10 +#define NFDATA (*((volatile unsigned char *)0x4E000010)) 11 +#define NFSTAT (*((volatile unsigned char *)0x4E000020)) 12 + 13 +/* CLK */ 14 +#define CLKDIVN (*(volatile unsigned long *)0x4C000014) 15 +#define MPLLCON (*(volatile unsigned long *)0x4C000004) 16 + 17 +/* SDRAM */ 18 +#define BWSCON (*(volatile unsigned long *)0x48000000) 19 +#define BANKCON6 (*(volatile unsigned long *)0x4800001c) 20 +#define REFRESH (*(volatile unsigned long *)0x48000024) 21 +#define BANKSIZE (*(volatile unsigned long *)0x48000028) 22 +#define MRSRB6 (*(volatile unsigned long *)0x4800002c) 23 + 24 +void init_clock(void) 25 +{ 26 + //Mpll = 400M 27 + MPLLCON = (0x5c<<12) | (1<<4) | 1; 28 + //FCLK 400M HCLK 100M PCLK 50M 29 + CLKDIVN = 2<<1 | 1<<0; 30 + __asm__( 31 + "mrc p15,0,r0,c1,c0,0\n" 32 + "orr r0,r0,#0xc0000000\n" 33 + "mcr p15,0,r0,c1,c0,0\n" 34 + ); 35 +} 36 + 37 +void init_sdram(void) 38 +{ 39 + BWSCON = 1<<25; 40 + BANKCON6 = 1<<16 | 1<<15 | 1; 41 + REFRESH = (1<<23) + 1268; 42 + BANKSIZE = 1<<7 | 1<<4 | 1; 43 + MRSRB6 = 0x30; 44 +} 45 + 46 +void clear_bss(void) 47 +{ 48 + extern int __bss_start, __bss_end; 49 + int *p = &__bss_start; 50 + 51 + for (; p < &__bss_end; p++) 52 + { 53 + *p = 0; 54 + } 55 +} 56 + 57 +static void nand_latency(void) 58 +{ 59 + int i=100; 60 + while(i--); 61 +} 62 + 63 +static void nand_is_ready(void) 64 +{ 65 + //bit 0 : 1 不忙了 66 + while(! (NFSTAT & 1)); 67 +} 68 + 69 +static void nand_write_addr(unsigned int addr) 70 +{ 71 + int col, page; 72 + col = addr % 2048; 73 + page = addr / 2048; 74 + 75 + NFADDR = col & 0xff; /* Column Address A0~A7 */ 76 + nand_latency(); 77 + NFADDR = (col >> 8) & 0x0f; /* Column Address A8~A11 */ 78 + nand_latency(); 79 + NFADDR = page & 0xff; /* Row Address A12~A19 */ 80 + nand_latency(); 81 + NFADDR = (page >> 8) & 0xff; /* Row Address A20~A27 */ 82 + nand_latency(); 83 + NFADDR = (page >> 16) & 0x03; /* Row Address A28~A29 */ 84 + nand_latency(); 85 +} 86 + 87 +static unsigned char nand_read_char(void) 88 +{ 89 + //只保留8个bit 90 + return NFDATA & 0xff; 91 +} 92 + 93 +static void nand_cmd(unsigned char cmd) 94 +{ 95 + NFCMMD = cmd; 96 + nand_latency(); 97 +} 98 + 99 +static void nand_select_chip(void) 100 +{ 101 + //1bit : 0 选中 102 + NFCONT &= ~(1<<1); 103 +} 104 + 105 +static void nand_deselect_chip(void) 106 +{ 107 + //1bit : 1 选中 108 + NFCONT |= (1<<1); 109 +} 110 + 111 +static void nand_reset(void) 112 +{ 113 + nand_select_chip(); 114 + nand_cmd(0xff); 115 + nand_deselect_chip(); 116 +} 117 + 118 +void nand_init_ll(void) 119 +{ 120 + //TACLS 3.3v 时 12ns 121 + #define TACLS 0 122 + //12ns 123 + #define TWRPH0 1 124 + //5ns 125 + #define TWRPH1 0 126 + NFCONF = TACLS<<12 | TWRPH0<<8 | TWRPH1<<4; 127 + /* 4 ECC 128 + * 1 CE 先不选中，用的时候在选中 129 + * 0 启动 flash controller 130 + */ 131 + NFCONT = 1<<4 | 1<<1 | 1; 132 + nand_reset(); 133 +} 134 + 135 +static void nand_read(unsigned int addr, unsigned char *buf, int len) 136 +{ 137 + //选中 138 + nand_select_chip(); 139 + //j 地址可能不是从0对齐开始读的 140 + unsigned int i = addr,j = addr % 2048; 141 + for(; i<(addr + len);) 142 + { 143 + //读命令 144 + nand_cmd(0x00); 145 + nand_is_ready(); 146 + 147 + //发送地址 148 + nand_write_addr(i); 149 + nand_is_ready(); 150 + 151 + //在次发出读命令 152 + nand_cmd(0x30); 153 + nand_is_ready(); 154 + //读2K 155 + for(; j<2048; j++) 156 + { 157 + *buf = nand_read_char(); 158 + buf++; 159 + i++; 160 + } 161 + j=0; 162 + nand_latency(); 163 + } 164 + //取消选中 165 + nand_deselect_chip(); 166 +} 167 + 168 +static int boot_is_nor() 169 +{ 170 + //利用 NOR 不能写的特点判断 171 + volatile unsigned int *p = (volatile unsigned int *)0; 172 + unsigned int val; 173 + val = *p; 174 + *p = 0x12345678; 175 + if(0x12345678 == *p) 176 + { 177 + *p = val; 178 + return 0; 179 + } 180 + return 1; 181 +} 182 + 183 +//片内4K 的程序要复制到链接SDRAM中去 184 +void copy_code_to_sdram(unsigned char *src,unsigned char *dst,int len) 185 +{ 186 + int i = 0; 187 + if(boot_is_nor()) 188 + { 189 + while(i < len) 190 + { 191 + dst[i] = src[i]; 192 + i++; 193 + } 194 + } 195 + else 196 + { 197 + nand_read((int)src, dst, len); 198 + } 199 +} 200 + 201 diff -urN u-boot-2016.03/arch/arm/cpu/arm920t/Makefile u-boot-2016.03-ok/arch/arm/cpu/arm920t/Makefile 202 --- u-boot-2016.03/arch/arm/cpu/arm920t/Makefile 2016-03-14 22:20:21.000000000 +0800 203 +++ u-boot-2016.03-ok/arch/arm/cpu/arm920t/Makefile 2016-05-17 06:48:31.767626866 +0800 204 @@ -8,6 +8,7 @@ 205 extra-y = start.o 206 207 obj-y += cpu.o 208 +obj-y += init.o 209 obj-$(CONFIG_USE_IRQ) += interrupts.o 210 211 obj-$(CONFIG_EP93XX) += ep93xx/ 212 diff -urN u-boot-2016.03/arch/arm/cpu/arm920t/start.S u-boot-2016.03-ok/arch/arm/cpu/arm920t/start.S 213 --- u-boot-2016.03/arch/arm/cpu/arm920t/start.S 2016-03-14 22:20:21.000000000 +0800 214 +++ u-boot-2016.03-ok/arch/arm/cpu/arm920t/start.S 2016-05-17 06:48:31.782641369 +0800 215 @@ -82,11 +82,50 @@ 216 217 /* FCLK:HCLK:PCLK = 1:2:4 */ 218 /* default FCLK is 120 MHz ! */ 219 - ldr r0, =CLKDIVN 220 - mov r1, #3 221 - str r1, [r0] 222 + //ldr r0, =CLKDIVN 223 + //mov r1, #3 224 + //str r1, [r0] 225 + 226 + /* 设置分频参数 */ 227 + ldr r0, =CLKDIVN 228 + mov r1, #0x05; /* FCLK:HCLK:PCLK=1:4:8 */ 229 + str r1, [r0] 230 + 231 + /* 如果HDIVN非0，CPU的总线模式应该从“fast bus mode”变为“asynchronous bus mode” */ 232 + mrc p15, 0, r1, c1, c0, 0 /* 读出控制寄存器 */ 233 + orr r1, r1, #0xc0000000 /* 设置为“asynchronous bus mode” */ 234 + mcr p15, 0, r1, c1, c0, 0 /* 写入控制寄存器 */ 235 + 236 + /* 配置时钟 */ 237 + #define S3C2440_MPLL_400MHZ ((0x5c<<12)|(0x01<<4)|(0x01)) 238 + ldr r0, =0x4c000004 239 + ldr r1, =S3C2440_MPLL_400MHZ 240 + str r1, [r0] 241 + 242 #endif /* CONFIG_S3C24X0 */ 243 244 + /** 245 + * 调用 init.c 中的初始化 246 + * 因为已经初始化好内存 所以 sp 在 顶部 247 + * 在 NOR 时不能用片内 4K 248 + */ 249 + ldr sp, =4096 250 + bl init_sdram 251 + ldr sp, =0x34000000 252 + bl nand_init_ll 253 + /** 254 + * 从 0 地址开始复制 到 SDRAM 中 255 + * 在 smdk2440.h 中定义 #define CONFIG_SYS_TEXT_BASE 256 + * u-boot 的加载地址 257 + */ 258 + mov r0,#0 259 + ldr r1, =CONFIG_SYS_TEXT_BASE 260 + ldr r2, =__bss_start 261 + sub r2, r2, r1 262 + bl copy_code_to_sdram 263 + bl clear_bss 264 + ldr pc, =_main 265 + 266 /* 267 * we do sys-critical inits only at reboot, 268 * not when booting from ram! 269 @@ -95,8 +134,6 @@ 270 bl cpu_init_crit 271 #endif 272 273 - bl _main 274 - 275 /*------------------------------------------------------------------------------*/ 276 277 .globl c_runtime_cpu_setup 278 diff -urN u-boot-2016.03/arch/arm/cpu/u-boot.lds u-boot-2016.03-ok/arch/arm/cpu/u-boot.lds 279 --- u-boot-2016.03/arch/arm/cpu/u-boot.lds 2016-03-14 22:20:21.000000000 +0800 280 +++ u-boot-2016.03-ok/arch/arm/cpu/u-boot.lds 2016-05-12 09:28:12.338040880 +0800 281 @@ -32,7 +32,7 @@ 282 */ 283 /DISCARD/ : { *(.rel._secure*) } 284 #endif 285 - . = 0x00000000; 286 + . = 0; 287 288 . = ALIGN(4); 289 .text : 290 diff -urN u-boot-2016.03/arch/arm/Kconfig u-boot-2016.03-ok/arch/arm/Kconfig 291 --- u-boot-2016.03/arch/arm/Kconfig 2016-03-14 22:20:21.000000000 +0800 292 +++ u-boot-2016.03-ok/arch/arm/Kconfig 2016-05-09 08:48:52.118143749 +0800 293 @@ -91,6 +91,10 @@ 294 config TARGET_SMDK2410 295 bool "Support smdk2410" 296 select CPU_ARM920T 297 + 298 +config TARGET_SMDK2440 299 + bool "Support smdk2440" 300 + select CPU_ARM920T 301 302 config TARGET_ASPENITE 303 bool "Support aspenite" 304 @@ -829,6 +833,7 @@ 305 source "board/phytec/pcm052/Kconfig" 306 source "board/ppcag/bg0900/Kconfig" 307 source "board/samsung/smdk2410/Kconfig" 308 +source "board/samsung/smdk2440/Kconfig" 309 source "board/sandisk/sansa_fuze_plus/Kconfig" 310 source "board/schulercontrol/sc_sps_1/Kconfig" 311 source "board/siemens/draco/Kconfig" 312 diff -urN u-boot-2016.03/arch/arm/lib/crt0.S u-boot-2016.03-ok/arch/arm/lib/crt0.S 313 --- u-boot-2016.03/arch/arm/lib/crt0.S 2016-03-14 22:20:21.000000000 +0800 314 +++ u-boot-2016.03-ok/arch/arm/lib/crt0.S 2016-05-16 17:11:44.287690421 +0800 315 @@ -99,7 +99,6 @@ 316 * relocate_code(addr_moni). Trick here is that we'll return 317 * 'here' but relocated. 318 */ 319 - 320 ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ 321 #if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */ 322 mov r3, sp 323 @@ -130,14 +129,17 @@ 324 325 bl c_runtime_cpu_setup /* we still call old routine here */ 326 #endif 327 + 328 + 329 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FRAMEWORK) 330 -# ifdef CONFIG_SPL_BUILD 331 +#ifdef CONFIG_SPL_BUILD 332 /* Use a DRAM stack for the rest of SPL, if requested */ 333 bl spl_relocate_stack_gd 334 cmp r0, #0 335 movne sp, r0 336 movne r9, r0 337 -# endif 338 +#endif 339 + 340 ldr r0, =__bss_start /* this is auto-relocated! */ 341 342 #ifdef CONFIG_USE_ARCH_MEMSET 343 @@ -177,3 +179,4 @@ 344 #endif 345 346 ENDPROC(_main) 347 + 348 diff -urN u-boot-2016.03/arch/arm/lib/relocate.S u-boot-2016.03-ok/arch/arm/lib/relocate.S 349 --- u-boot-2016.03/arch/arm/lib/relocate.S 2016-03-14 22:20:21.000000000 +0800 350 +++ u-boot-2016.03-ok/arch/arm/lib/relocate.S 2016-05-16 17:11:48.481661370 +0800 351 @@ -26,6 +26,7 @@ 352 353 ENTRY(relocate_vectors) 354 355 + 356 #ifdef CONFIG_CPU_V7M 357 /* 358 * On ARMv7-M we only have to write the new vector address 359 diff -urN u-boot-2016.03/board/samsung/smdk2440/Kconfig u-boot-2016.03-ok/board/samsung/smdk2440/Kconfig 360 --- u-boot-2016.03/board/samsung/smdk2440/Kconfig 1970-01-01 07:00:00.000000000 +0700 361 +++ u-boot-2016.03-ok/board/samsung/smdk2440/Kconfig 2016-05-16 21:51:04.391251360 +0800 362 @@ -0,0 +1,15 @@ 363 +if TARGET_SMDK2440 364 + 365 +config SYS_BOARD 366 + default "smdk2440" 367 + 368 +config SYS_VENDOR 369 + default "samsung" 370 + 371 +config SYS_SOC 372 + default "s3c24x0" 373 + 374 +config SYS_CONFIG_NAME 375 + default "smdk2440" 376 + 377 +endif 378 diff -urN u-boot-2016.03/board/samsung/smdk2440/lowlevel_init.S u-boot-2016.03-ok/board/samsung/smdk2440/lowlevel_init.S 379 --- u-boot-2016.03/board/samsung/smdk2440/lowlevel_init.S 1970-01-01 07:00:00.000000000 +0700 380 +++ u-boot-2016.03-ok/board/samsung/smdk2440/lowlevel_init.S 2016-05-16 21:51:04.246938015 +0800 381 @@ -0,0 +1,147 @@ 382 +/* 383 + * Memory Setup stuff - taken from blob memsetup.S 384 + * 385 + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and 386 + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) 387 + * 388 + * Modified for the Samsung SMDK2410 by 389 + * (C) Copyright 2002 390 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> 391 + * 392 + * SPDX-License-Identifier: GPL-2.0+ 393 + */ 394 + 395 + 396 +#include <config.h> 397 + 398 +/* some parameters for the board */ 399 + 400 +/* 401 + * 402 + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S 403 + * 404 + * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com> 405 + * 406 + */ 407 + 408 +#define BWSCON 0x48000000 409 + 410 +/* BWSCON */ 411 +#define DW8 (0x0) 412 +#define DW16 (0x1) 413 +#define DW32 (0x2) 414 +#define WAIT (0x1<<2) 415 +#define UBLB (0x1<<3) 416 + 417 +#define B1_BWSCON (DW32) 418 +#define B2_BWSCON (DW16) 419 +#define B3_BWSCON (DW16 + WAIT + UBLB) 420 +#define B4_BWSCON (DW16) 421 +#define B5_BWSCON (DW16) 422 +#define B6_BWSCON (DW32) 423 +#define B7_BWSCON (DW32) 424 + 425 +/* BANK0CON */ 426 +#define B0_Tacs 0x0 /* 0clk */ 427 +#define B0_Tcos 0x0 /* 0clk */ 428 +#define B0_Tacc 0x7 /* 14clk */ 429 +#define B0_Tcoh 0x0 /* 0clk */ 430 +#define B0_Tah 0x0 /* 0clk */ 431 +#define B0_Tacp 0x0 432 +#define B0_PMC 0x0 /* normal */ 433 + 434 +/* BANK1CON */ 435 +#define B1_Tacs 0x0 /* 0clk */ 436 +#define B1_Tcos 0x0 /* 0clk */ 437 +#define B1_Tacc 0x7 /* 14clk */ 438 +#define B1_Tcoh 0x0 /* 0clk */ 439 +#define B1_Tah 0x0 /* 0clk */ 440 +#define B1_Tacp 0x0 441 +#define B1_PMC 0x0 442 + 443 +#define B2_Tacs 0x0 444 +#define B2_Tcos 0x0 445 +#define B2_Tacc 0x7 446 +#define B2_Tcoh 0x0 447 +#define B2_Tah 0x0 448 +#define B2_Tacp 0x0 449 +#define B2_PMC 0x0 450 + 451 +#define B3_Tacs 0x0 /* 0clk */ 452 +#define B3_Tcos 0x3 /* 4clk */ 453 +#define B3_Tacc 0x7 /* 14clk */ 454 +#define B3_Tcoh 0x1 /* 1clk */ 455 +#define B3_Tah 0x0 /* 0clk */ 456 +#define B3_Tacp 0x3 /* 6clk */ 457 +#define B3_PMC 0x0 /* normal */ 458 + 459 +#define B4_Tacs 0x0 /* 0clk */ 460 +#define B4_Tcos 0x0 /* 0clk */ 461 +#define B4_Tacc 0x7 /* 14clk */ 462 +#define B4_Tcoh 0x0 /* 0clk */ 463 +#define B4_Tah 0x0 /* 0clk */ 464 +#define B4_Tacp 0x0 465 +#define B4_PMC 0x0 /* normal */ 466 + 467 +#define B5_Tacs 0x0 /* 0clk */ 468 +#define B5_Tcos 0x0 /* 0clk */ 469 +#define B5_Tacc 0x7 /* 14clk */ 470 +#define B5_Tcoh 0x0 /* 0clk */ 471 +#define B5_Tah 0x0 /* 0clk */ 472 +#define B5_Tacp 0x0 473 +#define B5_PMC 0x0 /* normal */ 474 + 475 +#define B6_MT 0x3 /* SDRAM */ 476 +#define B6_Trcd 0x1 477 +#define B6_SCAN 0x1 /* 9bit */ 478 + 479 +#define B7_MT 0x3 /* SDRAM */ 480 +#define B7_Trcd 0x1 /* 3clk */ 481 +#define B7_SCAN 0x1 /* 9bit */ 482 + 483 +/* REFRESH parameter */ 484 +#define REFEN 0x1 /* Refresh enable */ 485 +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ 486 +#define Trp 0x0 /* 2clk */ 487 +#define Trc 0x3 /* 7clk */ 488 +#define Tchr 0x2 /* 3clk */ 489 +#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ 490 +/**************************************/ 491 + 492 +.globl lowlevel_init 493 +lowlevel_init: 494 + /* memory control configuration */ 495 + /* make r0 relative the current location so that it */ 496 + /* reads SMRDATA out of FLASH rather than memory ! */ 497 + ldr r0, =SMRDATA 498 + ldr r1, =CONFIG_SYS_TEXT_BASE 499 + sub r0, r0, r1 500 + ldr r1, =BWSCON /* Bus Width Status Controller */ 501 + add r2, r0, #13*4 502 +0: 503 + ldr r3, [r0], #4 504 + str r3, [r1], #4 505 + cmp r2, r0 506 + bne 0b 507 + 508 + /* everything is fine now */ 509 + mov pc, lr 510 + 511 + .ltorg 512 +/* the literal pools origin */ 513 + 514 +SMRDATA: 515 + .long 0x22011110 //BWSCON 516 + .long 0x00000700 //BANKCON0 517 + .long 0x00000700 //BANKCON1 518 + .long 0x00000700 //BANKCON2 519 + .long 0x00000700 //BANKCON3 520 + .long 0x00000740 //BANKCON4 521 + .long 0x00000700 //BANKCON5 522 + .long 0x00018005 //BANKCON6 523 + .long 0x00018005 //BANKCON7 524 + .long 0x008C04F4 // REFRESH 525 + .long 0x000000B1 //BANKSIZE 526 + .long 0x00000030 //MRSRB6 527 + .long 0x00000030 //MRSRB7 528 + 529 diff -urN u-boot-2016.03/board/samsung/smdk2440/MAINTAINERS u-boot-2016.03-ok/board/samsung/smdk2440/MAINTAINERS 530 --- u-boot-2016.03/board/samsung/smdk2440/MAINTAINERS 1970-01-01 07:00:00.000000000 +0700 531 +++ u-boot-2016.03-ok/board/samsung/smdk2440/MAINTAINERS 2016-05-16 21:51:04.335323843 +0800 532 @@ -0,0 +1,6 @@ 533 +SMDK2440 BOARD 534 +M: David M眉ller <d.mueller@elsoft.ch> 535 +S: Maintained 536 +F: board/samsung/smdk2440/ 537 +F: include/configs/smdk2440.h 538 +F: configs/smdk2440_defconfig 539 diff -urN u-boot-2016.03/board/samsung/smdk2440/Makefile u-boot-2016.03-ok/board/samsung/smdk2440/Makefile 540 --- u-boot-2016.03/board/samsung/smdk2440/Makefile 1970-01-01 07:00:00.000000000 +0700 541 +++ u-boot-2016.03-ok/board/samsung/smdk2440/Makefile 2016-05-16 21:51:04.451323638 +0800 542 @@ -0,0 +1,9 @@ 543 +# 544 +# (C) Copyright 2000-2006 545 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. 546 +# 547 +# SPDX-License-Identifier: GPL-2.0+ 548 +# 549 + 550 +obj-y := smdk2440.o 551 +obj-y += lowlevel_init.o 552 diff -urN u-boot-2016.03/board/samsung/smdk2440/smdk2440.c u-boot-2016.03-ok/board/samsung/smdk2440/smdk2440.c 553 --- u-boot-2016.03/board/samsung/smdk2440/smdk2440.c 1970-01-01 07:00:00.000000000 +0700 554 +++ u-boot-2016.03-ok/board/samsung/smdk2440/smdk2440.c 2016-05-16 21:51:04.267044306 +0800 555 @@ -0,0 +1,138 @@ 556 +/* 557 + * (C) Copyright 2002 558 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 559 + * Marius Groeger <mgroeger@sysgo.de> 560 + * 561 + * (C) Copyright 2002, 2010 562 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> 563 + * 564 + * SPDX-License-Identifier: GPL-2.0+ 565 + */ 566 + 567 +#include <common.h> 568 +#include <netdev.h> 569 +#include <asm/io.h> 570 +#include <asm/arch/s3c24x0_cpu.h> 571 + 572 +DECLARE_GLOBAL_DATA_PTR; 573 + 574 +#define FCLK_SPEED 1 575 + 576 +#if (FCLK_SPEED == 0) /* Fout = 203MHz, Fin = 12MHz for Audio */ 577 +#define M_MDIV 0xC3 578 +#define M_PDIV 0x4 579 +#define M_SDIV 0x1 580 +#elif (FCLK_SPEED == 1) /* Fout = 202.8MHz */ 581 +#define M_MDIV 0xA1 582 +#define M_PDIV 0x3 583 +#define M_SDIV 0x1 584 +#endif 585 + 586 +#define USB_CLOCK 1 587 + 588 +#if (USB_CLOCK == 0) 589 +#define U_M_MDIV 0xA1 590 +#define U_M_PDIV 0x3 591 +#define U_M_SDIV 0x1 592 +#elif (USB_CLOCK == 1) 593 +#define U_M_MDIV 0x48 594 +#define U_M_PDIV 0x3 595 +#define U_M_SDIV 0x2 596 +#endif 597 + 598 +static inline void pll_delay(unsigned long loops) 599 +{ 600 + __asm__ volatile ("1:\n" 601 + "subs %0, %1, #1\n" 602 + "bne 1b" : "=r" (loops) : "0" (loops)); 603 +} 604 + 605 +/* 606 + * Miscellaneous platform dependent initialisations 607 + */ 608 + 609 +int board_early_init_f(void) 610 +{ 611 + struct s3c24x0_clock_power * const clk_power = 612 + s3c24x0_get_base_clock_power(); 613 + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); 614 + 615 + /* to reduce PLL lock time, adjust the LOCKTIME register */ 616 + writel(0xFFFFFF, &clk_power->locktime); 617 + 618 + /* configure MPLL */ 619 + //writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon); 620 + 621 + /* some delay between MPLL and UPLL */ 622 + //pll_delay(4000); 623 + 624 + /* configure UPLL */ 625 + writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, 626 + &clk_power->upllcon); 627 + 628 + /* some delay between MPLL and UPLL */ 629 + pll_delay(8000); 630 + 631 + /* set up the I/O ports */ 632 + writel(0x007FFFFF, &gpio->gpacon); 633 + writel(0x00044555, &gpio->gpbcon); 634 + writel(0x000007FF, &gpio->gpbup); 635 + writel(0xAAAAAAAA, &gpio->gpccon); 636 + writel(0x0000FFFF, &gpio->gpcup); 637 + writel(0xAAAAAAAA, &gpio->gpdcon); 638 + writel(0x0000FFFF, &gpio->gpdup); 639 + writel(0xAAAAAAAA, &gpio->gpecon); 640 + writel(0x0000FFFF, &gpio->gpeup); 641 + writel(0x000055AA, &gpio->gpfcon); 642 + writel(0x000000FF, &gpio->gpfup); 643 + writel(0xFF95FFBA, &gpio->gpgcon); 644 + writel(0x0000FFFF, &gpio->gpgup); 645 + writel(0x002AFAAA, &gpio->gphcon); 646 + writel(0x000007FF, &gpio->gphup); 647 + 648 + return 0; 649 +} 650 + 651 +int board_init(void) 652 +{ 653 + /* arch number of SMDK2410-Board */ 654 + gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; 655 + 656 + /* adress of boot parameters */ 657 + gd->bd->bi_boot_params = 0x30000100; 658 + 659 + icache_enable(); 660 + dcache_enable(); 661 + 662 + return 0; 663 +} 664 + 665 +int dram_init(void) 666 +{ 667 + /* dram_init must store complete ramsize in gd->ram_size */ 668 + gd->ram_size = PHYS_SDRAM_1_SIZE; 669 + return 0; 670 +} 671 + 672 +#ifdef CONFIG_CMD_NET 673 +int board_eth_init(bd_t *bis) 674 +{ 675 + int rc = 0; 676 +#ifdef CONFIG_CS8900 677 + rc = cs8900_initialize(0, CONFIG_CS8900_BASE); 678 +#endif 679 + return rc; 680 +} 681 +#endif 682 + 683 +/* 684 + * Hardcoded flash setup: 685 + * Flash 0 is a non-CFI AMD AM29LV800BB flash. 686 + */ 687 +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) 688 +{ 689 + info->portwidth = FLASH_CFI_16BIT; 690 + info->chipwidth = FLASH_CFI_BY16; 691 + info->interface = FLASH_CFI_X16; 692 + return 1; 693 +} 694 diff -urN u-boot-2016.03/configs/smdk2440_defconfig u-boot-2016.03-ok/configs/smdk2440_defconfig 695 --- u-boot-2016.03/configs/smdk2440_defconfig 1970-01-01 07:00:00.000000000 +0700 696 +++ u-boot-2016.03-ok/configs/smdk2440_defconfig 2016-05-09 07:56:48.822806092 +0800 697 @@ -0,0 +1,4 @@ 698 +CONFIG_ARM=y 699 +CONFIG_TARGET_SMDK2440=y 700 +CONFIG_SYS_PROMPT="SMDK2440 # " 701 +# CONFIG_CMD_SETEXPR is not set 702 diff -urN u-boot-2016.03/include/configs/smdk2410.h u-boot-2016.03-ok/include/configs/smdk2410.h 703 --- u-boot-2016.03/include/configs/smdk2410.h 2016-03-14 22:20:21.000000000 +0800 704 +++ u-boot-2016.03-ok/include/configs/smdk2410.h 2016-05-12 08:31:46.907513241 +0800 705 @@ -18,10 +18,10 @@ 706 * (easy to change) 707 */ 708 #define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ 709 -#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ 710 +#define CONFIG_S3C2440 711 #define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */ 712 713 -#define CONFIG_SYS_TEXT_BASE 0x0 714 +#define CONFIG_SYS_TEXT_BASE 0x33f00000 715 716 717 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH 718 @@ -49,16 +49,16 @@ 719 /************************************************************ 720 * USB support (currently only works with D-cache off) 721 ************************************************************/ 722 -#define CONFIG_USB_OHCI 723 -#define CONFIG_USB_OHCI_S3C24XX 724 -#define CONFIG_USB_KEYBOARD 725 -#define CONFIG_USB_STORAGE 726 -#define CONFIG_DOS_PARTITION 727 +/*#define CONFIG_USB_OHCI */ 728 +/*#define CONFIG_USB_OHCI_S3C24XX */ 729 +/*#define CONFIG_USB_KEYBOARD */ 730 +/*#define CONFIG_USB_STORAGE */ 731 +/*#define CONFIG_DOS_PARTITION */ 732 733 /************************************************************ 734 * RTC 735 ************************************************************/ 736 -#define CONFIG_RTC_S3C24X0 737 +/*#define CONFIG_RTC_S3C24X0*/ 738 739 740 #define CONFIG_BAUDRATE 115200 741 @@ -66,22 +66,22 @@ 742 /* 743 * BOOTP options 744 */ 745 -#define CONFIG_BOOTP_BOOTFILESIZE 746 -#define CONFIG_BOOTP_BOOTPATH 747 -#define CONFIG_BOOTP_GATEWAY 748 -#define CONFIG_BOOTP_HOSTNAME 749 +/*#define CONFIG_BOOTP_BOOTFILESIZE*/ 750 +/*#define CONFIG_BOOTP_BOOTPATH*/ 751 +/*#define CONFIG_BOOTP_GATEWAY*/ 752 +/*#define CONFIG_BOOTP_HOSTNAME*/ 753 754 /* 755 * Command line configuration. 756 */ 757 -#define CONFIG_CMD_BSP 758 +/*#define CONFIG_CMD_BSP*/ 759 #define CONFIG_CMD_CACHE 760 -#define CONFIG_CMD_DATE 761 -#define CONFIG_CMD_DHCP 762 +/*#define CONFIG_CMD_DATE*/ 763 +/*#define CONFIG_CMD_DHCP*/ 764 #define CONFIG_CMD_NAND 765 #define CONFIG_CMD_PING 766 -#define CONFIG_CMD_REGINFO 767 -#define CONFIG_CMD_USB 768 +/*#define CONFIG_CMD_REGINFO*/ 769 +/*#define CONFIG_CMD_USB*/ 770 771 #define CONFIG_SYS_HUSH_PARSER 772 #define CONFIG_CMDLINE_EDITING 773 @@ -93,8 +93,8 @@ 774 #define CONFIG_ZERO_BOOTDELAY_CHECK 775 776 #define CONFIG_NETMASK 255.255.255.0 777 -#define CONFIG_IPADDR 10.0.0.110 778 -#define CONFIG_SERVERIP 10.0.0.1 779 +#define CONFIG_IPADDR 192.168.1.88 780 +#define CONFIG_SERVERIP 192.168.1.1 781 782 #if defined(CONFIG_CMD_KGDB) 783 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ 784 @@ -167,24 +167,27 @@ 785 * NAND configuration 786 */ 787 #ifdef CONFIG_CMD_NAND 788 -#define CONFIG_NAND_S3C2410 789 -#define CONFIG_SYS_S3C2410_NAND_HWECC 790 #define CONFIG_SYS_MAX_NAND_DEVICE 1 791 #define CONFIG_SYS_NAND_BASE 0x4E000000 792 +#define CONFIG_NAND_S3C2440 793 +#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING 794 +#define CONFIG_S3C24XX_TACLS 1 795 +#define CONFIG_S3C24XX_TWRPH0 2 796 +#define CONFIG_S3C24XX_TWRPH1 1 797 #endif 798 799 /* 800 * File system 801 */ 802 -#define CONFIG_CMD_FAT 803 -#define CONFIG_CMD_EXT2 804 -#define CONFIG_CMD_UBI 805 -#define CONFIG_CMD_UBIFS 806 +/*#define CONFIG_CMD_FAT*/ 807 +/*#define CONFIG_CMD_EXT2*/ 808 +/*#define CONFIG_CMD_UBI*/ 809 +/*#define CONFIG_CMD_UBIFS*/ 810 #define CONFIG_CMD_MTDPARTS 811 #define CONFIG_MTD_DEVICE 812 #define CONFIG_MTD_PARTITIONS 813 #define CONFIG_YAFFS2 814 -#define CONFIG_RBTREE 815 +/*#define CONFIG_RBTREE*/ 816 817 /* additions for new relocation code, must be added to all boards */ 818 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 819 diff -urN u-boot-2016.03/include/configs/smdk2440.h u-boot-2016.03-ok/include/configs/smdk2440.h 820 --- u-boot-2016.03/include/configs/smdk2440.h 1970-01-01 07:00:00.000000000 +0700 821 +++ u-boot-2016.03-ok/include/configs/smdk2440.h 2016-05-16 17:39:51.777785587 +0800 822 @@ -0,0 +1,157 @@ 823 +/* 824 + * (C) Copyright 2002 825 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 826 + * Marius Groeger <mgroeger@sysgo.de> 827 + * Gary Jennejohn <garyj@denx.de> 828 + * David Mueller <d.mueller@elsoft.ch> 829 + * 830 + * Configuation settings for the SAMSUNG SMDK2440 board. 831 + * 832 + * SPDX-License-Identifier: GPL-2.0+ 833 + */ 834 + 835 +#ifndef __CONFIG_H 836 +#define __CONFIG_H 837 + 838 +/* 839 + * High Level Configuration Options 840 + * (easy to change) 841 + */ 842 +#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ 843 +#define CONFIG_S3C2440 /* specifically a SAMSUNG S3C2440 SoC */ 844 +#define CONFIG_SMDK2440 /* on a SAMSUNG SMDK2440 Board */ 845 + 846 +#define CONFIG_SYS_TEXT_BASE 0x30a00000/*0x33f00000*/ 847 + 848 + 849 +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH 850 + 851 +/* input clock of PLL (the SMDK2440 has 12MHz input clock) */ 852 +#define CONFIG_SYS_CLK_FREQ 12000000 853 + 854 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 855 +#define CONFIG_SETUP_MEMORY_TAGS 856 +#define CONFIG_INITRD_TAG 857 + 858 +/* 859 + * Hardware drivers 860 + */ 861 + 862 +/* 863 + * select serial console configuration 864 + */ 865 +#define CONFIG_S3C24X0_SERIAL 866 +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2440 */ 867 + 868 + 869 + 870 +#define CONFIG_BAUDRATE 115200 871 + 872 +/* 873 + * BOOTP options 874 + */ 875 +#define CONFIG_BOOTP_BOOTFILESIZE 876 +#define CONFIG_BOOTP_BOOTPATH 877 +#define CONFIG_BOOTP_GATEWAY 878 +#define CONFIG_BOOTP_HOSTNAME 879 + 880 + 881 +#define CONFIG_CMD_PING 882 +#define CONFIG_SYS_HUSH_PARSER 883 +#define CONFIG_CMDLINE_EDITING 884 + 885 +/* autoboot */ 886 +#define CONFIG_BOOTDELAY 5 887 +#define CONFIG_BOOT_RETRY_TIME -1 888 +#define CONFIG_RESET_TO_RETRY 889 +#define CONFIG_ZERO_BOOTDELAY_CHECK 890 + 891 +#define CONFIG_NETMASK 255.255.255.0 892 +#define CONFIG_IPADDR 192.168.1.123 893 +#define CONFIG_SERVERIP 192.168.1.100 894 + 895 +#if defined(CONFIG_CMD_KGDB) 896 +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ 897 +#endif 898 + 899 +/* 900 + * Miscellaneous configurable options 901 + */ 902 +#define CONFIG_SYS_LONGHELP /* undef to save memory */ 903 +#define CONFIG_SYS_CBSIZE 256 904 +/* Print Buffer Size */ 905 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 906 + sizeof(CONFIG_SYS_PROMPT)+16) 907 +#define CONFIG_SYS_MAXARGS 16 908 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 909 + 910 +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ 911 + 912 +#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ 913 +#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ 914 + 915 +#define CONFIG_SYS_LOAD_ADDR 0x30800000 916 + 917 +/* support additional compression methods */ 918 +#define CONFIG_BZIP2 919 +#define CONFIG_LZO 920 +#define CONFIG_LZMA 921 + 922 +/*----------------------------------------------------------------------- 923 + * Physical Memory Map 924 + */ 925 +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 926 +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ 927 +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 928 + 929 +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #0 */ 930 + 931 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 932 + 933 +/*----------------------------------------------------------------------- 934 + * FLASH and environment organization 935 + */ 936 + 937 +#define CONFIG_SYS_FLASH_CFI 938 +#define CONFIG_FLASH_CFI_DRIVER 939 +#define CONFIG_FLASH_CFI_LEGACY 940 +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 941 +#define CONFIG_FLASH_SHOW_PROGRESS 45 942 + 943 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 944 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 945 +#define CONFIG_SYS_MAX_FLASH_SECT (19) 946 + 947 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) 948 +#define CONFIG_ENV_IS_IN_FLASH 949 +#define CONFIG_ENV_SIZE 0x10000 950 +/* allow to overwrite serial and ethaddr */ 951 +#define CONFIG_ENV_OVERWRITE 952 + 953 +/* 954 + * Size of malloc() pool 955 + * BZIP2 / LZO / LZMA need a lot of RAM 956 + */ 957 +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 958 + 959 +#define CONFIG_SYS_MONITOR_LEN (448 * 1024) 960 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 961 + 962 +/* 963 + * NAND configuration 964 + */ 965 +#ifdef CONFIG_CMD_NAND 966 +#define CONFIG_NAND_S3C2440 967 +#define CONFIG_SYS_S3C2440_NAND_HWECC 968 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 969 +#define CONFIG_SYS_NAND_BASE 0x4E000000 970 +#endif 971 + 972 +/* additions for new relocation code, must be added to all boards */ 973 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 974 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 975 + GENERATED_GBL_DATA_SIZE) 976 + 977 +#define CONFIG_BOARD_EARLY_INIT_F 978 + 979 +#endif /* __CONFIG_H */ 980 diff -urN u-boot-2016.03/Makefile u-boot-2016.03-ok/Makefile 981 --- u-boot-2016.03/Makefile 2016-03-14 22:20:21.000000000 +0800 982 +++ u-boot-2016.03-ok/Makefile 2016-05-09 08:38:00.046292963 +0800 983 @@ -7,7 +7,8 @@ 984 SUBLEVEL = 985 EXTRAVERSION = 986 NAME = 987 - 988 +ARCH=arm 989 +CROSS_COMPILE=arm-linux- 990 # *DOCUMENTATION* 991 # To see a list of typical targets execute "make help" 992 # More info can be located in ./README 993 Binary files u-boot-2016.03/.swp and u-boot-2016.03-ok/.swp differ
