USRP Daugherboard: DBSRX

USRP Daugherboard: DBSRX

下面是一DBSRX子板的介绍。

Specifications

RX: 800MHz - 2.4GHz

TX: N/A

Notes

This section contains a collection of notes regarding the DBSRX daughterboard.

The frequency range and maximum and minimum bandwidth given in the MAX2118 is different from the one stated in the datasheet from www.ettus.com. Matt Ettus explains the differences:

Frequency Range

The MAX2118 datasheet says that it covers 925 to 2175 MHz. They spec that because it is the range that their typical customer needs (for small satellite dish IFs). However, I have never found one which doesn't work to the larger 800 MHz to 2400 MHz range. Maxim guarantees 925 to 2175, I guarantee the larger range.

我一开始也觉得奇怪，因为我看数据手册，很明晰MAX2118的datasheet频率是850到2175，旧版的是925到2175，但是这个板子是800到2400MHz。结果这里解释了，说可以在800到2400内工作，而且做了保证。

Bandwidth

When Maxim states that their maximum LPF bandwidth is 33 MHz, they mean one-sided bandwidth (i.e. 0 to 33 MHz). Since it is used in a direct conversion IQ system, that actually gives a 66 MHz bandwidth (-33 MHz to +33 MHz). Since that is beyond Nyquist for our ADC, I spec to 60 MHz (+/- 30 MHz).

On the low end, they specify 4 MHz, which is really 8 MHz (+/-4 MHz) of RF bandwidth. The filter is actually capable of going to a much narrow frequency, but it is outside of Maxim's specs, since nobody in the small satellite dish market cares about less than 8 MHz of BW. So I spec that it goes down to 1 MHz wide. It should be noted that when you go below 4 MHz wide (2 MHz in Maxim-speak) that your noise floor will rise a bit and phase noise may also rise.

Tuning

Taken from an email to discuss-gnuradio on 27 Mar 2007 from Gregory W Heckler:

Tuning the down-converter on the DBS-RX card consists of programming the values of 2 dividers. The R divider divides down the reference clock frequency (4 MHz, which derives from the 64 MHz board clock). The N divider divides down the LO frequency. The R divider has a range from 2 to 256, the N divider from 256 to 32768. The Max2118 phase locks the divided LO frequency to the divided reference clock frequency, or:

LO = N*(Refclk_Freq/R)

However, the PLL in the Max2118 is unstable if you divide down the reference clock frequency to below 250 kHz, this effectively limits the frequency resolution at which you can command the LO frequency.

Antenna bias

Taken from an email to discuss-gnuradio on 11 Jul 2007 from Matt Ettus:

Shorting J101 puts 5 Volts (up to 500 mA I believe) on the antenna line. Applying voltage to J100 pin 1 allows you to send bias other than 5V.

Block Diagram¶

Nice Block diagram produced by Gregory W Heckler.

 

 看过原理图后初步分析：

先是信号从天线进来，到一个MGA82563的0.1-6G 3V，17dBm 的放大器，然后进入MAX2118

( MAX2116/MAX2118系列低成本直接变频调谐器芯片是为数字卫星直播(DBS)电视系统、专业的VSAT (超小孔径终端)系统和双向“卫星因特网”应用设计的。本器件用宽带I/Q下变频器将L波段信号直接变频至基带。工作频率范围从925MHz到2175MHz。)

这个芯片主要做一个工作：把高频信号下变频到IF，然后通过USRP1中的AD去对IF复数信号进行采样，同时USRP1里边的FPGA还要对IF做处理，使其搬移到基带。最后通过PC对基带信号做处理。

在这个子板中，做DDC处理是用复数，可以这么理解:

f(t)e^(-jw0t)  为了把信号搬移到w0处

然后在频域上：

F(w)*§（w-w0）=F（w-w0）

在时域上的运算等于：  f(t)e^(-jw0t)  =  1/2 X f(t) X (cosw0t - j sinw0t)，所以输出有实数和虚数。

一般我们下变频是乘以cosw0t，但是如果乘以cosw0t的话，欧拉公式分解后可知，在频域上就会出现正负的频率谱，负频谱对我们来说是没有任何作用的。所以现在用复数来下变频，就只出现单边谱。

 

接下来就是到USRP1的FPGA再做IF的DDC处理。