k60系统时钟
K60系统时钟源,转载的留下学习和参考
飞思卡尔 Kinetis系列是飞思卡尔推出的基于ARM CORTEX-M4为核心的微控制器。
1.飞思卡尔K60时钟系统
![](http://images0.cnblogs.com/blog/463984/201302/24094845-800cc2fcb9da47a0a723acf23de9fdf6.png)
飞思卡尔K60时钟系统如上图所示,可以发现器件的源时钟源一共有4个:
①内部参考时钟源,包括 Fast IRC和 slow IRC (IRC--Internal Reference Clock)
②外部参考时钟源,只一个EXTAL管脚作为时钟输入,这个可以使用有源晶体振荡器来实现
③外部晶体谐振器,使用EXTAL和XTAL两个管脚来输入
④外部32K RTC 谐振器,用于实时时钟的时钟输入
在图中可以看到,要为系统提供时钟信号,关键是要最终生成 MCGOUTCLK 输出。MCGOUTCLK 再经过分频便可以提供Core/system clocks、Bus clock、FlexBus clock和Flash clock。MCGOUTCLK 的产生有3个途径:
①由内部参考时钟源 Fast IRC 直接提供,这个时钟源集成在芯片的内部(包括Slow IRC),频率是2M
②由 FLL 或者 PLL 模块来提供
③由外部时钟来直接提供,包括外部参考时钟源(1个管脚输入)、外部晶体谐振器经内部OSC logic产生的XTAL_CLK 和 RTC OSC logic 的时钟输出。
一般情况下,MCGOUTCLK 是由PLL或者FLL倍频来产生的,飞思卡尔官方的例程最终是由PLL模块来产生。图中可以看到PLL模块的时钟输入是OSCCLK或者RTC OSC logic。我的板子以外部参考时钟源提供PLL时钟,最终经PLL倍频产生MCGOUTCLK。即 EXTAL-->PLL模块-->MCGOUTCLK.
2.关于时钟模式
从图中可以看到,该芯片一共包含8种工作时钟模式,外加Stop模式。系统在RESET后直接进入默认的FEI模式。图中,F--FLL、P--PLL、E--Enable或者EXTAL(外部时钟)、B--Bypass(旁路)、I--Internal(内部参考时钟)、L--Low Power.
·FLL 启用、内部参考时钟(FEI), 内部参考时钟提供FLL的时钟,FLL驱动MCGOUT
·FLL 启用、外部参考时钟(FEE), 外部参考时钟提供FLL的时钟,FLL驱动MCGOUT
·FLL 旁路、内部参考时钟(FBI),FLL虽然在运作但由内部时钟参考源驱动MCGOUT
·FLL 旁路、外部参考时钟(FBE),FLL虽然在运作但由外部时钟参考源驱动MCGOUT
·PLL 旁路、外部参考时钟(PBE),PLL虽然在运作但由外部时钟参考源驱动MCGOUT
·PLL 启用、外部参考时钟(PEE),外部参考时钟提供PLL的时钟,PLL驱动MCGOUT
·BLPI FLL和PLL都禁用,内部时钟参考源驱动MCGOUT
·BLPE FLL和PLL都禁用,外部时钟参考源驱动MCGOUT
由于系统在重启后默认进入FEI模式,我们的目标是要跳到PEE模式,所以要涉及到模式的转化。图中由FEI到PEE是不能直接跳转的,必须经由其他模式来转换。
3.官方具体的例子
来源于飞思卡尔官方\src\drivers\mcg\mcg.c
- unsigned char pll_init(unsigned char clk_option, unsigned char crystal_val)
- {
- unsigned char pll_freq;
- if (clk_option > 3) {return 0;} //return 0 if one of the available options is not selected
- if (crystal_val > 15) {return 1;} // return 1 if one of the available crystal options is not available
- //This assumes that the MCG is in default FEI mode out of reset.
- // First move to FBE mode
- #if (defined(K60_CLK) || defined(ASB817))
- MCG_C2 = 0;
- #else
- // Enable external oscillator, RANGE=2, HGO=1, EREFS=1, LP=0, IRCS=0
- MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;
- #endif
- // after initialization of oscillator release latched state of oscillator and GPIO
- SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;
- LLWU_CS |= LLWU_CS_ACKISO_MASK;
- // Select external oscilator and Reference Divider and clear IREFS to start ext osc
- // CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
- MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
- /* if we aren't using an osc input we don't need to wait for the osc to init */
- #if (!defined(K60_CLK) && !defined(ASB817))
- while (!(MCG_S & MCG_S_OSCINIT_MASK)){}; // wait for oscillator to initialize
- #endif
- while (MCG_S & MCG_S_IREFST_MASK){}; // wait for Reference clock Status bit to clear
- while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status bits to show clock source is ext ref clk
- // Now in FBE
- #if (defined(K60_CLK))
- //MCG_C5 = MCG_C5_PRDIV(0x18);
- MCG_C5 = MCG_C5_PRDIV(0x18); //基频2M 外部时钟源是50M时, 50/25=2M
- #else
- // Configure PLL Ref Divider, PLLCLKEN=0, PLLSTEN=0, PRDIV=5
- // The crystal frequency is used to select the PRDIV value. Only even frequency crystals are supported
- // that will produce a 2MHz reference clock to the PLL.
- MCG_C5 = MCG_C5_PRDIV(crystal_val); // Set PLL ref divider to match the crystal used
- #endif
- // Ensure MCG_C6 is at the reset default of 0. LOLIE disabled, PLL disabled, clk monitor disabled, PLL VCO divider is clear
- MCG_C6 = 0x0;
- // Select the PLL VCO divider and system clock dividers depending on clocking option
- switch (clk_option) {
- case 0:
- // Set system options dividers
- //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
- set_sys_dividers(0,0,0,1);
- // Set the VCO divider and enable the PLL for 50MHz, LOLIE=0, PLLS=1, CME=0, VDIV=1
- MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(1); //VDIV = 1 (x25)
- pll_freq = 50;
- break;
- case 1:
- // Set system options dividers
- //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
- set_sys_dividers(0,1,1,3);
- // Set the VCO divider and enable the PLL for 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
- MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(26); //VDIV = 26 (x50)
- pll_freq = 100;
- break;
- case 2:
- // Set system options dividers
- //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
- set_sys_dividers(0,1,1,3);
- // Set the VCO divider and enable the PLL for 96MHz, LOLIE=0, PLLS=1, CME=0, VDIV=24
- MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48)
- pll_freq = 96;
- break;
- case 3:
- // Set system options dividers
- //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
- set_sys_dividers(0,0,0,1);
- // Set the VCO divider and enable the PLL for 48MHz, LOLIE=0, PLLS=1, CME=0, VDIV=0
- MCG_C6 = MCG_C6_PLLS_MASK; //VDIV = 0 (x24)
- pll_freq = 48;
- break;
- }
- while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
- while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
- // Now running PBE Mode
- // Transition into PEE by setting CLKS to 0
- // CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
- MCG_C1 &= ~MCG_C1_CLKS_MASK;
- // Wait for clock status bits to update
- while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
- // Now running PEE Mode
- return pll_freq;
- } //pll_init