摘要: ++++++++++++++++++++++++++++++++++++++++++本文系本站原创,欢迎转载! 转载请注明出处:http://blog.csdn.net/mr_raptor/article/details/6442914++++++++++++++++++++++++++++++++++++++++++1.PHASE LOCKED LOOP(PLL)S3C6410里包含三个PLL(锁相环),APLL, MPLL, EPLL,通过设置它们将输入时钟同步输出达到操作CPU的工作频率的目的。如图1-1所示。Voltage Controlled Oscillator (VCO)P[5: 阅读全文
posted @ 2011-05-24 17:13 little_raptor 阅读(3286) 评论(0) 推荐(0) 编辑