| 1111 |
194 |
184 |
4 hours ago |
ghdl/1 |
VHDL 2008/93/87 simulator |
| 1014 |
376 |
7 |
3 hours ago |
aws-fpga/2 |
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit |
| 924 |
461 |
15 |
7 years ago |
Open-Source-FPGA-Bitcoin-Miner/3 |
A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards. |
| 744 |
36 |
1 |
4 years ago |
FPGA_Webserver/4 |
A work-in-progress for what is to be a software-free web server for static content. |
| 499 |
115 |
6 |
6 years ago |
gplgpu/5 |
GPL v3 2D/3D graphics engine in verilog |
| 388 |
156 |
119 |
8 days ago |
vunit/6 |
VUnit is a unit testing framework for VHDL/SystemVerilog |
| 381 |
169 |
5 |
2 years ago |
parallella-hw/7 |
Parallella board design files |
| 377 |
139 |
3 |
3 years ago |
parallella-examples/8 |
Community created parallella projects |
| 341 |
54 |
7 |
a month ago |
gcvideo/9 |
GameCube Digital AV converter |
| 337 |
81 |
32 |
8 months ago |
PoC/10 |
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany |
| 331 |
67 |
23 |
4 months ago |
mist-board/11 |
Core sources and tools for the MIST board |
| 323 |
54 |
17 |
15 days ago |
nvc/12 |
VHDL compiler and simulator |
| 311 |
80 |
21 |
3 months ago |
f32c/13 |
A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz |
| 283 |
88 |
9 |
1 year, 4 months ago |
dsi-shield/14 |
Arduino MIPI DSI Shield |
| 266 |
32 |
29 |
4 days ago |
hal/15 |
HAL – The Hardware Analyzer |
| 240 |
31 |
6 |
10 months ago |
opl3_fpga/16 |
Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer |
| 238 |
77 |
2 |
1 year, 10 months ago |
CSI2Rx/17 |
Open Source 4k CSI-2 Rx core for Xilinx FPGAs |
| 201 |
32 |
4 |
5 days ago |
a2i/18 |
None |
| 200 |
16 |
0 |
5 months ago |
forth-cpu/19 |
A Forth CPU and System on a Chip, based on the J1, written in VHDL |
| 174 |
34 |
2 |
4 years ago |
FPGA_DisplayPort/20 |
An implementation of DisplayPort protocol for FPGAs |
| 164 |
15 |
12 |
4 days ago |
ghdl-yosys-plugin/21 |
VHDL synthesis (based on ghdl) |
| 162 |
51 |
8 |
14 hours ago |
UVVM/22 |
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/ |
| 157 |
28 |
2 |
a month ago |
potato/23 |
A simple RISC-V processor for use in FPGA designs. |
| 157 |
59 |
8 |
22 days ago |
Vitis-Tutorials/24 |
None |
| 142 |
18 |
0 |
4 years ago |
space-invaders-vhdl/25 |
Space Invaders game implemented with VHDL |
| 135 |
40 |
5 |
2 years ago |
hardh264/26 |
A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx. |
| 135 |
41 |
1 |
2 years ago |
vna2/27 |
Second version of homemade 30 MHz - 6 GHz VNA |
| 129 |
27 |
1 |
1 year, 9 months ago |
tinyTPU/28 |
Implementation of a Tensor Processing Unit for embedded systems and the IoT. |
| 128 |
38 |
15 |
10 days ago |
OSVVM/29 |
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ... |
| 128 |
20 |
14 |
5 days ago |
fletcher/30 |
Fletcher: A framework to integrate FPGA accelerators with Apache Arrow |
| 122 |
50 |
2 |
3 years ago |
VHDL_Lib/31 |
Library of VHDL components that are useful in larger designs. |
| 112 |
23 |
1 |
5 years ago |
zpu/32 |
The Zylin ZPU |
| 112 |
32 |
185 |
a month ago |
mega65-core/33 |
MEGA65 FPGA core |
| 111 |
24 |
0 |
5 years ago |
neppielight/34 |
FPGA-based HDMI ambient lighting |
| 110 |
51 |
1 |
11 months ago |
fmcw3/35 |
Two RX-channel 6 GHz FMCW radar design files |
| 108 |
4 |
5 |
5 months ago |
FPGBA/36 |
GBA on FPGA |
| 108 |
24 |
14 |
3 days ago |
rust_hdl/37 |
None |
| 106 |
16 |
1 |
19 days ago |
neo430/38 |
A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL. |
| 106 |
13 |
0 |
10 months ago |
nexys4ddr/39 |
Various projects for the Nexys4DDR board from Digilent |
| 104 |
16 |
4 |
a month ago |
C64-Video-Enhancement/40 |
Component video modification for the C64 8-bit computer |
| 102 |
42 |
8 |
1 year, 7 months ago |
Artix-7-HDMI-processing/41 |
Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA |
| 100 |
26 |
0 |
4 years ago |
HDMI2USB-jahanzeb-firmware/42 |
Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project |
| 94 |
30 |
0 |
11 months ago |
XJTU-Tripler/43 |
This repository is the backup of XJTU-Tripler project, participating dac19 system design contest |
| 93 |
61 |
14 |
1 year, 7 months ago |
Cosmos-plus-OpenSSD/44 |
Cosmos OpenSSD + Hardware and Software source distribution |
| 89 |
11 |
2 |
1 year, 10 months ago |
freezing-spice/45 |
A pipelined RISCV implementation in VHDL |
| 89 |
26 |
4 |
2 years ago |
vhdl-extras/46 |
Flexible VHDL library |
| 89 |
14 |
0 |
a day ago |
un0rick/47 |
smallish ice40 / raspberrypi ultrasound hardware |
| 88 |
10 |
2 |
a month ago |
hdl4fpga/48 |
VHDL library 4 FPGAs |
| 85 |
7 |
1 |
4 years ago |
TPU/49 |
TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+. |
| 82 |
8 |
0 |
11 months ago |
greta/50 |
GRETA expansion board for the Amiga 500 computer with Fast RAM, microSD mass storage and Ethernet controller, powered by FPGA technology. |
| 82 |
36 |
0 |
3 years ago |
ethernet_mac/51 |
Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL |
| 82 |
41 |
7 |
7 days ago |
SNES_MiSTer/52 |
SNES for MiSTer |
| 81 |
19 |
2 |
1 year, 6 months ago |
PYNQ-DL/53 |
Xilinx Deep Learning IP |
| 80 |
39 |
1 |
4 years ago |
hard-cv/54 |
A repository of IPs for hardware computer vision (FPGA) |
| 79 |
31 |
1 |
7 years ago |
ZynqBTC/55 |
A Bitcoin miner for the Zynq chip utilizing the Zedboard. |
| 79 |
48 |
1 |
2 years ago |
ZPUino-HDL/56 |
ZPUino HDL implementation |
| 74 |
37 |
55 |
a day ago |
axiom-firmware/57 |
AXIOM firmware (linux image, gateware and software tools) |
| 73 |
6 |
0 |
25 days ago |
RPU/58 |
Basic RISC-V CPU implementation in VHDL. |
| 69 |
11 |
17 |
1 year, 1 month ago |
w11/59 |
PDP-11/70 CPU core and SoC |
| 68 |
3 |
1 |
6 years ago |
yafc/60 |
Yet Another Forth Core... |
| 68 |
15 |
9 |
1 year, 1 month ago |
bladeRF-adsb/61 |
bladeRF ADS-B hardware decoder |
| 68 |
12 |
5 |
11 months ago |
AtomBusMon/62 |
This project is an open-source In-Circuit Emulator for the 6502, 65C02, Z80, 6809 and 6809E 8-bit processors. See: |
| 67 |
33 |
0 |
2 years ago |
Simon_Speck_Ciphers/63 |
Implementations of the Simon and Speck Block Ciphers |
| 66 |
11 |
3 |
9 days ago |
sdram-fpga/64 |
A FPGA core for a simple SDRAM controller. |
| 64 |
72 |
2 |
3 years ago |
Digital-Design-Lab/65 |
None |
| 64 |
49 |
2 |
4 months ago |
LimeSDR-USB_GW/66 |
Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board |
| 62 |
42 |
1 |
2 months ago |
Hackster/67 |
Files used with hackster examples |
| 60 |
21 |
1 |
4 months ago |
iCE40HX1K-EVB/68 |
FPGA development board made with KiCAD |
| 59 |
46 |
9 |
4 years ago |
logi-projects/69 |
None |
| 58 |
40 |
3 |
3 years ago |
sublime-vhdl/70 |
VHDL Package for Sublime Text |
| 58 |
20 |
2 |
6 years ago |
Arduino-Soft-Core/71 |
None |
| 55 |
7 |
1 |
2 years ago |
q27/72 |
27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting |
| 55 |
25 |
5 |
3 months ago |
haddoc2/73 |
Caffe to VHDL |
| 54 |
17 |
0 |
2 years ago |
Hardware_Neural_Net/74 |
Artificial Neural Network in hardware |
| 53 |
18 |
10 |
12 days ago |
esp/75 |
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy |
| 52 |
20 |
9 |
3 months ago |
GBA_MiSTer/76 |
GBA for MiSTer |
| 51 |
12 |
0 |
3 years ago |
RFToolSDR/77 |
AD9361 based USB3 SDR |
| 51 |
30 |
1 |
4 years ago |
uart/78 |
A VHDL UART for communicating over a serial link with an FPGA |
| 50 |
22 |
1 |
6 months ago |
IIoT-EDDP/79 |
The repository contains the design database and documentation for Electric Drives Demonstration Platform |
| 50 |
10 |
0 |
2 years ago |
vpcie/80 |
implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture |
| 49 |
21 |
0 |
6 years ago |
FPGA-Oscilloscope/81 |
Design, Documentation, Schematic, Board, Code files for the FPGA Oscilloscope project using an Altera Cyclone III FPGA. |
| 48 |
12 |
4 |
2 years ago |
spi-fpga/82 |
SPI master and slave for FPGA written in VHDL |
| 48 |
17 |
1 |
6 years ago |
FpgasNowWhat/83 |
Source for the "FPGAs?! Now What?" Book |
| 47 |
17 |
0 |
3 years ago |
fpga-multi-effect/84 |
FPGA-based Multi-Effects system for the electric guitar |
| 46 |
25 |
1 |
1 year, 6 months ago |
spi-master/85 |
SPI Master for FPGA - VHDL and Verilog |
| 46 |
30 |
0 |
14 days ago |
TurboGrafx16_MiSTer/86 |
TurboGrafx-16 CD / PC Engine CD for MiSTer |
| 46 |
4 |
0 |
a month ago |
bit-serial/87 |
A bit-serial CPU written in VHDL, with a simulator written in C. |
| 45 |
14 |
3 |
6 years ago |
libv/88 |
Useful set of library functions for VHDL |
| 44 |
7 |
0 |
a month ago |
jt51/89 |
YM2151 clone in verilog. FPGA proven. |
| 44 |
22 |
2 |
3 years ago |
Vivado-KMeans/90 |
Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs |
| 44 |
25 |
1 |
2 years ago |
SiaFpgaMiner/91 |
VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin |
| 43 |
9 |
6 |
2 years ago |
ReonV/92 |
ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA. |
| 43 |
67 |
8 |
4 months ago |
mlib_devel/93 |
None |
| 42 |
9 |
1 |
1 year, 8 months ago |
CoPro6502/94 |
FPGA implementations of BBC Micro Co Processors (65C02, Z80, 6809, 68000, x86, ARM2, PDP-11, 32016) |
| 41 |
29 |
0 |
7 years ago |
VHDL/95 |
VHDL Samples |
| 41 |
8 |
2 |
8 months ago |
JSON-for-VHDL/96 |
A JSON library implemented in VHDL. |
| 41 |
26 |
7 |
5 years ago |
Papilio-Arcade/97 |
A collection of arcade games targeted for Papilio FPGA boards. Many of the games are from FPGAArcade.com. |
| 41 |
26 |
10 |
a month ago |
Gameboy_MiSTer/98 |
Gameboy for MiSTer |
| 41 |
15 |
0 |
3 days ago |
zxuno/99 |
None |
| 41 |
100 |
3 |
3 years ago |
Basys3/100 |
None |
| 41 |
21 |
3 |
6 days ago |
surf/101 |
A huge VHDL library for FPGA development |
| 40 |
15 |
20 |
2 years ago |
HDMI2USB-numato-opsis-sample-code/102 |
Example code for the Numato Opsis board, the first HDMI2USB production board. |
| 40 |
19 |
4 |
7 days ago |
Vitis-In-Depth-Tutorial/103 |
None |
| 40 |
5 |
2 |
8 months ago |
Rudi-RV32I/104 |
A rudimental RISCV CPU supporting RV32I instructions, in VHDL |
| 40 |
21 |
1 |
a year ago |
fpgagen/105 |
SEGA Genesis/Megadrive core, running on a Altera/Terasic DE1 board. |
| 39 |
30 |
1 |
8 months ago |
LimeSDR-Mini_GW/106 |
LimeSDR-Mini board FPGA project |
| 38 |
26 |
1 |
11 months ago |
FPGA-I2C-Minion/107 |
A simple I2C minion in VHDL |
| 38 |
22 |
9 |
5 months ago |
C64_MiSTer/108 |
None |
| 37 |
11 |
3 |
21 days ago |
A-VideoBoard/109 |
FPGA board to create a component video signal for vintage computers. |
| 38 |
19 |
2 |
23 days ago |
Mist_FPGA/110 |
None |
| 37 |
6 |
0 |
18 days ago |
awesome-model-quantization/111 |
A list of papers, docs, codes about model quantization. This repo is aimed to provide the info for model quantization research, we are continuously improving the project. Welcome to PR the works (papers, repositories) that are missed by the repo. |
| 37 |
27 |
0 |
4 years ago |
ODriveFPGA/112 |
High performance motor control |
| 37 |
13 |
3 |
2 months ago |
leros/113 |
A Tiny Processor Core |
| 37 |
14 |
0 |
4 months ago |
CNN_for_SLR/114 |
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA. |
| 36 |
4 |
1 |
4 months ago |
1bitSDR/115 |
Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom |
| 35 |
4 |
0 |
8 months ago |
fpga-fft/116 |
A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm |
| 35 |
54 |
0 |
8 months ago |
FPGA/117 |
FPGA |
| 35 |
6 |
2 |
3 months ago |
FlowBlaze/118 |
FlowBlaze: Stateful Packet Processing in Hardware |
| 35 |
8 |
4 |
a day ago |
phywhispererusb/119 |
PhyWhisperer-USB: Hardware USB Trigger |
| 34 |
5 |
2 |
4 hours ago |
wasca/120 |
Sega Saturn multipurporse cartridge |
| 32 |
11 |
2 |
2 years ago |
mce2vga/121 |
MDA/CGA/EGA to VGA FPGA Converter V2.00 |
| 32 |
13 |
0 |
4 years ago |
fpga-spectrum/122 |
Sinclair ZX Spectrum 48k and 128k on an Altera DE1 FPGA board |
| 31 |
10 |
0 |
6 years ago |
FPGAPCE/123 |
PC-Engine / Turbografx-16 clone running on an Altera DE1 board. |
| 31 |
19 |
0 |
5 years ago |
MIPS-processor/124 |
MIPS processor designed in VHDL |
| 30 |
7 |
5 |
15 days ago |
BeebFpga/125 |
None |
| 30 |
25 |
3 |
6 months ago |
rfsoc_qpsk/126 |
None |
| 30 |
18 |
2 |
2 months ago |
Zybo-Z7-20-pcam-5c/127 |
None |
| 30 |
15 |
0 |
2 years ago |
FPGA-Speech-Recognition/128 |
Expiremental Speech Recognition System using VHDL & MATLAB. |
| 30 |
21 |
0 |
2 years ago |
AX7010/129 |
None |
| 30 |
14 |
0 |
6 years ago |
XuLA/130 |
Everything to do with the XuLA FPGA board: schematics, layout, firmware, example FPGA designs, documentation, etc. |
| 29 |
11 |
0 |
4 years ago |
flearadio/131 |
Digital FM Radio Receiver for FPGA |
| 29 |
20 |
0 |
2 years ago |
jTDC/132 |
FPGA based 30ps RMS TDCs |
| 29 |
10 |
0 |
3 years ago |
openMixR/133 |
4k Mixed Reality headset |
| 29 |
6 |
1 |
2 years ago |
riscv-tomthumb/134 |
A small RISC-V RV32I core written in VHDL, intended as testbed for my personal VHDL learning |
| 29 |
11 |
0 |
9 months ago |
uart-for-fpga/135 |
Simple UART controller for FPGA written in VHDL |
| 29 |
14 |
0 |
6 years ago |
img_process_vhdl/136 |
Image Processing on FPGA using VHDL |
| 29 |
5 |
1 |
a day ago |
neorv32/137 |
A customizable, lightweight and open-source 32-bit RISC-V rv32imc + priv. arch. microcontroller/CPU written in platform-independent VHDL. |
| 28 |
8 |
0 |
7 years ago |
MIPS32/138 |
A MIPS32 CPU implemented by VHDL |
| 28 |
6 |
0 |
6 months ago |
flexray-interceptor/139 |
FPGA project to man-in-the-middle attack Flexray |
| 28 |
8 |
0 |
4 years ago |
rgb2vga/140 |
Analog RGB 15Khz to VGA 31Khz in FGPA |
| 28 |
12 |
0 |
a month ago |
intfftk/141 |
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0. |
| 28 |
1 |
0 |
4 years ago |
Sweet32-CPU/142 |
Sweet32 32bit MRISC CPU - VHDL and software toolchain sources (including documentation) |
| 27 |
8 |
0 |
13 hours ago |
scaffold/143 |
Donjon hardware tool for circuits security evaluation |
| 27 |
15 |
0 |
5 months ago |
tinycrypt/144 |
Crypto stuff. Don't use. |
| 27 |
7 |
1 |
4 years ago |
FPGA_GigabitTx/145 |
Sending UDP packets out over a Gigabit PHY with an FPGA. |
| 26 |
1 |
0 |
8 months ago |
router/146 |
清华大学2019计网联合实验第一组 |
| 27 |
22 |
3 |
5 years ago |
altera-de2-ann/147 |
Artificial Neural Network on Altera DE2 |
| 27 |
8 |
2 |
3 months ago |
AtomFpga/148 |
Dave's version of the Acorn Atom FPGA, based on AlanD's original from stardot.org.uk |
| 27 |
4 |
0 |
10 days ago |
fos/149 |
FOS - FPGA Operating System |
| 27 |
10 |
2 |
3 years ago |
fphdl/150 |
VHDL-2008 Support Library |
| 27 |
7 |
0 |
11 months ago |
pano_man/151 |
Simulation of the classic Pacman arcade game on a PanoLogic thin client. |
| 26 |
14 |
0 |
30 days ago |
MultiComp/152 |
Spins of Grant Searle's MultiComp project on various hardware |
| 26 |
11 |
0 |
8 months ago |
Image-Processing/153 |
Image Processing Toolbox in Verilog using Basys3 FPGA |
| 26 |
1 |
0 |
6 years ago |
arm4u/154 |
ARM4U |
| 26 |
10 |
0 |
4 years ago |
FPGA-OV7670-cam/155 |
VHDL/FPGA/OV7670 |
| 26 |
10 |
0 |
8 years ago |
vhdl-nes/156 |
nes emulator based on VHDL |
| 26 |
193 |
0 |
2 years ago |
vivado-library/157 |
None |
| 26 |
12 |
0 |
2 years ago |
SpaceInvadersFpgaGame/158 |
Verilog implementation of the classic arcade game Space Invaders for the Zedboard FPGA board |
| 25 |
11 |
0 |
2 years ago |
FGPU/159 |
FGPU is a soft GPU architecture general purpose computing |
| 25 |
15 |
13 |
a month ago |
Orio/160 |
Orio is an open-source extensible framework for the definition of domain-specific languages and generation of optimized code for multiple architecture targets, including support for empirical autotuning of the generated code. |
| 25 |
3 |
0 |
3 years ago |
FPGA-radio/161 |
Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC |
| 25 |
12 |
0 |
2 years ago |
Designing-a-Custom-AXI-Slave-Peripheral/162 |
A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools |
| 25 |
1 |
0 |
1 year, 10 months ago |
MandelbrotInVHDL/163 |
What better way to learn VHDL, than to do some fractals? |
| 25 |
1 |
0 |
4 years ago |
fpga-vt/164 |
VT100-style terminal implemented on FPGA in VHDL |
| 24 |
1 |
0 |
5 months ago |
aes/165 |
AES-128 hardware implementation |
| 24 |
7 |
0 |
a month ago |
karabas-128/166 |
Karabas-128. ZX Spectrum 128k clone, based on CPLD Altera EPM7128STC100 |
| 24 |
19 |
0 |
5 years ago |
zynq_examples/167 |
None |
| 24 |
5 |
0 |
1 year, 11 months ago |
rtl-cheat/168 |
VHDL and Verilog minimal examples. IC design and synthesis tutorials. Asserts used wherever possible. |
| 24 |
8 |
1 |
2 years ago |
snickerdoodle-examples/169 |
Example projects for snickerdoodle |
| 24 |
24 |
11 |
a month ago |
SMS_MiSTer/170 |
Sega Master System for MiSTer |
| 24 |
9 |
0 |
4 years ago |
STREAM/171 |
FPGA development platform for high-performance RF and digital design |
| 23 |
12 |
0 |
Unknown |
FPGA-FAST/172 |
FPGA FAST image feature detector implementation in VHDL |
| 23 |
4 |
1 |
8 days ago |
AXI4/173 |
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components |
| 23 |
1 |
0 |
Unknown |
N.I.G.E.-Machine/174 |
A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is currently hosted on the Digilent Nexys 4 and Nexys 4 DDR |
| 23 |
10 |
0 |
6 years ago |
FP-V-GA-Text/175 |
A simple to use VHDL module to display text on VGA display. |
| 23 |
10 |
4 |
1 year, 9 months ago |
ppa-pcmcia-sram/176 |
PCMCIA SRAM card project (Sakura) |
| 23 |
29 |
3 |
4 years ago |
logi-hard/177 |
All Logi specific HDL code (platform specific interface, extension boards, specific hdl, etc) |
| 23 |
11 |
0 |
3 years ago |
FPGA_Neural-Network/178 |
The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the Neural Network part is meant to be generic, thus it can be used along with different hardware setups. |
| 23 |
17 |
5 |
2 years ago |
blockmon/179 |
A Modular System for Flexible, High-Performance Traffic http://www.ict-mplane.eu/ |
| 23 |
1 |
0 |
3 years ago |
from-key-array-to-the-LED-lattice/180 |
None |
| 23 |
7 |
1 |
a month ago |
AppleIISd/181 |
SD card based ProFile replacement for IIe |
| 23 |
5 |
2 |
5 years ago |
ZPUFlex/182 |
A highly-configurable and compact variant of the ZPU processor core |
| 23 |
8 |
0 |
a month ago |
fp23fftk/183 |
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL). |
| 23 |
2 |
0 |
4 months ago |
fpga-nat64/184 |
A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support. |
| 22 |
5 |
0 |
5 months ago |
X68000_MiSTer/185 |
Sharp X68000 for MiSTer |
| 22 |
16 |
0 |
1 year, 1 month ago |
mist-cores/186 |
core files for the MiST fpga |
| 22 |
4 |
2 |
Unknown |
Gauntlet_FPGA/187 |
FPGA implementation of Atari's Gauntlet arcade game |
| 22 |
2 |
0 |
Unknown |
noasic/188 |
An open-source VHDL library for FPGA design, licensed under the GNU lesser general public license. |
| 22 |
3 |
0 |
1 year, 7 days ago |
BenEaterVHDL/189 |
VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net) |
| 22 |
3 |
2 |
1 year, 4 months ago |
UnAmiga/190 |
Implementation of Amiga 500/1200 in Altera Cyclone IV FPGA |
| 22 |
19 |
0 |
4 years ago |
alpha-software/191 |
Axiom Alpha prototype software (FPGA, Linux, etc.) |
| 21 |
12 |
3 |
4 years ago |
OpenRIO/192 |
Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints. |
| 21 |
3 |
1 |
2 years ago |
whirlyfly/193 |
Hardware RNG for Papilio One based on the original Whirlygig |
| 21 |
6 |
0 |
2 years ago |
memsec/194 |
Framework for building transparent memory encryption and authentication solutions |
| 21 |
4 |
0 |
4 years ago |
opa/195 |
Open Processor Architecture |
| 21 |
13 |
3 |
2 months ago |
ahir/196 |
Algorithm to hardware compilation tools (e.g. C to VHDL). |
| 21 |
4 |
5 |
2 years ago |
MARK_II/197 |
Simple SoC in VHDL with full toolchain and custom board. |
| 21 |
26 |
17 |
10 months ago |
mksocfpga/198 |
Hostmot2 FPGA code for SoC/FPGA platforms from Altera and Xilinx |
| 21 |
3 |
8 |
2 months ago |
FPGA-robotics/199 |
Blocks for visual design of robot behaviors using FPGA and IceStudio |
| 21 |
8 |
1 |
10 months ago |
ZipML-XeonFPGA/200 |
FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware) |
| 21 |
1 |
0 |
4 years ago |
fpga-trace/201 |
FPGA accelerated ray tracer, implemented in C++ and HLS |
| 20 |
5 |
0 |
7 years ago |
robotron-fpga/202 |
FPGA implementation of Robotron: 2084 |
| 20 |
14 |
0 |
2 years ago |
MIPI_CSI2_TX/203 |
VHDL code for using Xilinx MGT gigabit transceivers/LVDS lines for MIPI CSI-2 TX protocol |
| 20 |
7 |
1 |
4 years ago |
VHDL-Pong/204 |
A Pong game written in VHDL using a Xilinx Spartan 3 board. VGA + PS/2 Keyboard + Sound support. |
| 20 |
5 |
0 |
5 months ago |
NTSC-composite-encoder/205 |
How to generate NTSC compliant(?) composite color video with an FPGA |
| 20 |
9 |
0 |
6 years ago |
Camera-Tracking/206 |
Our project is the system that enables a moving camera to track a moving object in real time. We plan on doing this by having a camera mounted to a swivel using two servo motors to allow for the camera’s direction to be controlled. The camera data will be read into the FPGA board and some basic object recognition algorithm will be used to identify an some object and determine if the camera needs to be moved to keep the object in the field of vision. In addition to the auto tracking mode, we plan on having an IR remote to allow for manual panning, mode selection, and power on and off. If there is additional time we would like to also interface the FPGA to a Raspberry Pi board running a linux web server to allow for email alerts (when object moves) and web based control. |
| 20 |
18 |
0 |
7 years ago |
rgbmatrix-fpga/207 |
Adafruit RGB LED Matrix Display Driver for use with FPGAs (written in VHDL) |
| 20 |
15 |
2 |
2 years ago |
Designing-a-Custom-AXI-Master-using-BFMs/208 |
A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models |
| 19 |
9 |
1 |
9 years ago |
Floating_Point_Library-JHU/209 |
VHDL for basic floating-point operations. |
| 19 |
5 |
6 |
1 year, 6 months ago |
EP994A/210 |
My TI-99/4A clone, two versions: FPGA+TMS99105 CPU and FPGA with my CPU core |
| 19 |
3 |
0 |
a month ago |
Xoodoo/211 |
None |
| 19 |
13 |
1 |
3 years ago |
fpga/212 |
VHDL description of the custom Demolicious GPU. Built during a single semester at NTNU |
| 19 |
6 |
0 |
2 years ago |
PoC-Examples/213 |
This repository contains synthesizable examples which use the PoC-Library. |
| 19 |
4 |
1 |
6 years ago |
BBot/214 |
BBot! An open source, wireless beer serving robot reference design featuring a C++ program running on a BeagleBone Black, a .Net WPF control GUI and even low level FPGA integration! |
| 19 |
6 |
0 |
1 year, 11 months ago |
PYNQ_softmax/215 |
achieve softmax in PYNQ with heterogeneous computing. |
| 19 |
10 |
0 |
5 months ago |
fpga_examples/216 |
Example code in vhdl to help starting new projects using FPGA devices. |
| 19 |
6 |
0 |
4 years ago |
PicoBlaze-Library/217 |
The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA). |
| 19 |
4 |
0 |
10 months ago |
secd/218 |
SECD microprocessor reimplementation in VHDL |
| 18 |
6 |
1 |
1 year, 1 month ago |
WishboneAXI/219 |
Wishbone to AXI bridge (VHDL) |
| 18 |
2 |
0 |
a day ago |
ArtyS7-RPU-SoC/220 |
Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board. |
| 18 |
7 |
0 |
5 years ago |
hdl/221 |
Collection of hardware description languages writings and code snippets |
| 18 |
1 |
14 |
7 days ago |
Codelib/222 |
None |
| 18 |
8 |
0 |
1 year, 11 months ago |
nesfpga/223 |
A Simple FPGA Implementation of the Nintendo Entertainment System |
| 18 |
6 |
0 |
1 year, 5 months ago |
fft/224 |
synthesizable FFT IP block for FPGA designs |
| 18 |
6 |
2 |
7 years ago |
dso-quad-usb-analyzer/225 |
USB Full-Speed (12Mbps) protocol analyzer for the DSO Quad |
| 18 |
7 |
6 |
6 years ago |
SimpleSDHC/226 |
A basic SD Card SPI interface in VHDL, supports SD V1, V2 and SDHC |
| 18 |
6 |
1 |
5 years ago |
la16fw/227 |
Alternative Logic16 Firmware |
| 18 |
7 |
0 |
1 year, 10 months ago |
vga_generator/228 |
A collection of VHDL projects for generating VGA output |
| 18 |
0 |
0 |
5 years ago |
C88/229 |
C88 is Homebrew CPU that has a ram that is only 8x8 Bits in size. It'll fit on a papilio one 500k which has enough pins for all the switches you need too. |
| 18 |
3 |
1 |
3 months ago |
PYNQ-Torch/230 |
PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform |
| 17 |
1 |
1 |
3 years ago |
NISC/231 |
A single instruction set processor architecture |
| 17 |
23 |
0 |
4 years ago |
Zedboard/232 |
None |
| 17 |
4 |
0 |
3 years ago |
Mips54/233 |
组成原理课程设计 |
| 17 |
16 |
3 |
3 days ago |
Atari2600_MiSTer/234 |
Atari 2600 for MiSTer |
| 17 |
7 |
0 |
7 years ago |
lemberg/235 |
Lemberg is a time-predictable VLIW processor optimized for performance. |
| 17 |
4 |
0 |
1 year, 7 months ago |
Motion-Detection-System-Based-On-Background-Reconstruction/236 |
This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to build a DMA based image data cache transmission system. On this basis, Verilog HDL was used to design the axi4-stream interface based IP core for image processing, so as to build a high real-time moving target detection system. In our design, we focus on the optimization of processing pipeline, improve the traditional frame difference method, and achieve the optimization goal of saving logical resources through the accumulation compression and reconstruction expansion of cached background frames. |
| 17 |
18 |
2 |
4 years ago |
StickIt/237 |
StickIt! board and modules that support the XuLA FPGA board. |
| 17 |
6 |
1 |
4 years ago |
VGA-Text-Generator/238 |
A basic VGA text generator for verilog and vhdl |
| 17 |
5 |
0 |
1 year, 5 months ago |
pid-fpga-vhdl/239 |
This project was part of the VLSI Lab. It implements PID control using an FPGA. |
| 17 |
5 |
11 |
5 years ago |
r-vex/240 |
A reconfigurable and extensible VLIW processor implemented in VHDL |
| 17 |
1 |
0 |
6 years ago |
myhdl_simple_uart/241 |
A very simple UART implementation in MyHDL |
| 17 |
5 |
0 |
5 months ago |
hd6309sbc/242 |
Hitachi HD6309 Singleboard Computer |
| 17 |
5 |
2 |
3 days ago |
cps2_digiav/243 |
CPS2 digital AV interface |
| 16 |
13 |
1 |
5 years ago |
zedboard_audio/244 |
A Audio Interface for the Zedboard |
| 16 |
12 |
1 |
7 years ago |
hashvoodoo-fpga-bitcoin-miner/245 |
HashVoodoo FPGA Bitcoin Miner |
| 16 |
19 |
0 |
3 years ago |
Nexys4DDR/246 |
None |
| 16 |
8 |
2 |
1 year, 10 months ago |
Nexys-4-DDR-OOB/247 |
None |
| 16 |
10 |
0 |
11 months ago |
Rattlesnake/248 |
PulseRain Rattlesnake - RISCV RV32IMC Soft CPU |
| 16 |
11 |
6 |
2 years ago |
OneChipMSX/249 |
A port of the OneChipMSX project to the Turbo Chameleon 64 and in time, hopefully other boards, too. |
| 16 |
9 |
1 |
2 years ago |
vcnn/250 |
Verilog Convolutional Neural Network on PYNQ |
| 16 |
8 |
0 |
8 months ago |
EP2C5-Cyclone-II-Mini-Board/251 |
EP2C5 Cyclone II Mini Board |
| 16 |
12 |
0 |
7 years ago |
grlib/252 |
None |
| 16 |
4 |
1 |
16 days ago |
dvb_fpga/253 |
RTL implementation of components for DVB-S2 |
| 16 |
8 |
3 |
4 months ago |
Apple-II_MiSTer/254 |
Apple II+ for MiSTer |
| 16 |
8 |
1 |
6 years ago |
cmake-verilog-vhdl-fpga-template/255 |
CMake template for Verilog and VHDL project and Altera/Xilinx FPGA target |
| 16 |
3 |
0 |
2 years ago |
THU-MIPS16-CPU/256 |
Tsinghua University Computer Composition Principle Experiment |
| 16 |
6 |
0 |
4 years ago |
zybo_petalinux_video_hls/257 |
Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output. |
| 16 |
2 |
1 |
1 year, 7 months ago |
ym2608/258 |
VHDL clone of YM2608 (OPNA) sound chip |
| 16 |
3 |
4 |
4 years ago |
tusSAT/259 |
A SAT solver implementation in VHDL, team tussle |
| 16 |
2 |
2 |
1 year, 2 months ago |
AladdinLCD/260 |
Convert the cheap AladdinXT 4032 Original Xbox modchip to an LCD driver for TSOP modded consoles. |
| 16 |
6 |
6 |
4 months ago |
Atari800_MiSTer/261 |
Atari 800XL/65XE/130XE for MiSTer |
| 15 |
4 |
0 |
4 years ago |
fpga-bbc/262 |
Acorn BBC Micro on an Altera DE1 FPGA board |
| 15 |
15 |
4 |
4 months ago |
MSX_MiSTer/263 |
MSX for MiSTer |
| 15 |
7 |
0 |
7 years ago |
c64pla/264 |
C64 PLA implementation in VHDL |
| 15 |
9 |
1 |
3 years ago |
Nexys4/265 |
None |
| 15 |
17 |
5 |
4 months ago |
PothosZynq/266 |
DMA source and sink blocks for Xilinx Zynq FPGAs |
| 15 |
3 |
0 |
5 days ago |
SneakySnake/267 |
SneakySnake🐍 is the first and the only pre-alignment filtering algorithm that works efficiently and fast on modern CPU, FPGA, and GPU architectures. It greatly (by more than two orders of magnitude) expedites sequence alignment calculation for both short (Illumina) and long (ONT and PacBio) reads. Described by Alser et al. (https://arxiv.org/abs/1910.09020). |
| 15 |
6 |
0 |
2 years ago |
revCtrl/268 |
Revision Control Labs and Materials |
| 15 |
6 |
4 |
2 years ago |
cv2PYNQ-The-project-behind-the-library/269 |
This project describes how the cv2PYNQ python library was built |
| 15 |
4 |
0 |
2 years ago |
Z-turn-examples/270 |
The repository with my simple Z-turn examples, to be used as templates for more serious project |
| 15 |
4 |
0 |
3 years ago |
Cache/271 |
Simple implementation of cache using VHDL |
| 15 |
5 |
0 |
6 years ago |
uart-vhdl/272 |
An RS232 communication controller implemented in VHDL |
| 15 |
3 |
0 |
5 years ago |
FPGA-LVDS-LCD-Hack/273 |
Basic code that displays simple shapes generated from Lattice FPGA directly to LVDS display |
| 15 |
10 |
1 |
3 years ago |
ZedBoard-OLED/274 |
Driving the OLED display on the ZedBoard |
| 15 |
2 |
0 |
2 months ago |
karabas-nano/275 |
Karabas Nano prototype |
| 14 |
2 |
1 |
6 months ago |
fpgaNES/276 |
None |
| 14 |
7 |
1 |
5 years ago |
axi_custom_ip_tb/277 |
A testbench for an axi lite custom IP |
| 14 |
5 |
0 |
2 years ago |
OSXA/278 |
The OSXA repository contains the design files for an LPC flash addon to the original xbox video game console. |
| 14 |
5 |
0 |
10 years ago |
MIPS-Lite/279 |
A pipelined MIPS-Lite CPU implementation |
| 14 |
3 |
0 |
2 years ago |
OSXANF/280 |
The OSXA repository contains the design files for a NOR flash addon to the original xbox video game console. |
| 14 |
9 |
0 |
8 years ago |
Network-on-Chip-in-VHDL/281 |
None |
| 14 |
7 |
0 |
a month ago |
vhdl_prng/282 |
Pseudo Random Number Generators as synthesizable VHDL code |
| 14 |
9 |
1 |
2 months ago |
Arcade-Arkanoid_MISTer/283 |
None |
| 14 |
0 |
0 |
6 months ago |
ese-vdp/284 |
VHDL implementation of YAMAHA V9938 |
| 14 |
8 |
2 |
3 years ago |
PYNQ_PR_Overlay/285 |
Adding PR to the PYNQ Overlay |
| 14 |
1 |
1 |
19 days ago |
psl_with_ghdl/286 |
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) |
| 14 |
9 |
0 |
1 year, 11 months ago |
sha256/287 |
A simple SHA-256 implementation in VHDL |
| 14 |
6 |
0 |
1 year, 5 months ago |
ReVerSE-U16/288 |
Development Kit |
| 14 |
3 |
0 |
3 years ago |
neuron-vhdl/289 |
Implementation of a neuron and 2 neuronal networks in vhdl |
| 13 |
7 |
3 |
a month ago |
msx1fpga/290 |
MSX1 cloned in FPGA |
| 13 |
6 |
0 |
2 months ago |
Altera-Cyclone-II-EP2C5T144-blink/291 |
A very junior "Hello World" for the low price Altera Cypress II EP2C5T144 FPGA Mini dev board from amazon/ebay |
| 13 |
6 |
0 |
2 years ago |
Spectrum/292 |
Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action. |
| 13 |
6 |
2 |
10 months ago |
pauloBlaze/293 |
A plain VHDL implementation of a small microprocessor fully compatible with the ISA of the well known PicoBlaze by Ken Chapman. |
| 14 |
7 |
5 |
4 months ago |
rygar-fpga/294 |
A FPGA core for the arcade game, Rygar (1986). |
| 13 |
9 |
0 |
3 years ago |
Hardware-Neural-Network/295 |
Embedded hardware accelerator of multilayer perceptrons for lightweight machine learning |
| 13 |
5 |
0 |
4 days ago |
BBCMicro_MiSTer/296 |
BBC Micro B and Master 128K for MiSTer |
| 13 |
5 |
1 |
7 months ago |
fmh_gpib_core/297 |
GPIB IEEE 488.1 core |
| 13 |
3 |
0 |
3 years ago |
subleq-machine-vhdl/298 |
The final code of a two-hour challenge to simulate and implement a SUBLEQ SISC machine |
| 13 |
12 |
4 |
5 months ago |
Arcade-DonkeyKong_MiSTer/299 |
Arcade: Donkey Kong for MiSTer |
| 13 |
4 |
0 |
2 years ago |
SMSMapper/300 |
Sega Master System Homebrew Flash Cart |
| 13 |
6 |
1 |
4 years ago |
FPGA_SDR/301 |
Software Defined Radio receiver in Marsohod2 Altera Cyclone III board |
| 13 |
2 |
0 |
5 years ago |
R-JTOP/302 |
Open source implementation of CB fusecheck glitch |
| 13 |
2 |
0 |
4 years ago |
vhdl2008-tester/303 |
Scripts to test which features from VHDL 2008 are supported by your compiler. |
| 13 |
0 |
0 |
2 years ago |
cosmac/304 |
RCA COSMAC CDP1802 functional equivalent CPU core in VHDL |
| 13 |
11 |
3 |
1 year, 5 months ago |
VHDL-JESD204b/305 |
JESD204b modules in VHDL |
| 13 |
5 |
1 |
a month ago |
WonderMadeleine/306 |
WonderMadeleine is a Bandai 2001/2003 clone chip |
| 13 |
7 |
0 |
9 months ago |
itc99-poli/307 |
ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino (I99T) |
| 13 |
11 |
0 |
9 months ago |
Hardware-Implementation-of-AES-VHDL/308 |
Hardware Implementation of Advanced Encryption Standard Algorithm in VHDL |
| 13 |
3 |
1 |
2 years ago |
ASP-SoC/309 |
Audio Signal Processing SoC |
| 13 |
19 |
0 |
4 months ago |
gnss-baseband/310 |
Baseband Receiver IP for GPS like DSSS signals |
| 13 |
6 |
0 |
2 years ago |
light52/311 |
Yet another free 8051 FPGA core |
| 13 |
2 |
0 |
2 days ago |
satcat5/312 |
SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network. |
| 12 |
0 |
3 |
17 days ago |
buryak-pi-2020/313 |
None |
| 12 |
2 |
1 |
5 years ago |
keyboard-ip/314 |
PS/2 Keyboard IP written in VHDL for Xilinx FPGA |
| 12 |
5 |
0 |
4 months ago |
jcore-soc/315 |
J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks. |
| 12 |
15 |
0 |
3 years ago |
zynq-dma/316 |
A Zynq DMA transfer project. linux code and vivado hardware design included. |
| 12 |
0 |
0 |
3 months ago |
FPGA-Audio-IIR/317 |
None |
| 12 |
2 |
0 |
2 years ago |
gs4502b/318 |
Experimental pipelined 4502 CPU design |
| 12 |
1 |
1 |
3 months ago |
Sudoku-Solver/319 |
A brute force algorithm on hardware is used to solve a sudoku. When a valid fill is not found backtracking is done. Backtracking is repeated until last number is a valid guess i.e guess out of 1 to 9. Digital logic realised using priority encoders and multiplexers. |
| 12 |
2 |
0 |
3 months ago |
FPGA-Class-D-Amplifier/320 |
None |
| 12 |
15 |
2 |
10 days ago |
Arcade-Pacman_MiSTer/321 |
Arcade: Pacman for MiSTer |
| 12 |
1 |
0 |
4 months ago |
fppa-pdk-emulator-vhdl/322 |
VHDL simulation model for PADAUK PDK microcontrollers |
| 12 |
5 |
1 |
3 years ago |
netv2-fpga-basic-overlay/323 |
Vivado design for basic NeTV2 FPGA with chroma-based overlay |
| 12 |
6 |
2 |
3 days ago |
TG68K.C/324 |
switchable 68K CPU-Core |
| 12 |
3 |
1 |
4 months ago |
AES-VHDL/325 |
VHDL Implementation of AES Algorithm |
| 12 |
2 |
0 |
11 years ago |
zpu/326 |
ZPU - the worlds smallest 32 bit CPU with GCC toolchain |
| 12 |
0 |
0 |
4 years ago |
YM2612/327 |
VHDL description and documentation of architecture and undocumented features in Yamaha YM2203 (OPN) and YM2612 (OPN2) |
| 12 |
2 |
0 |
6 years ago |
myhdl-examples/328 |
None |
| 12 |
3 |
0 |
5 years ago |
GAIA3/329 |
GAIA Processor |
| 12 |
1 |
0 |
3 years ago |
gimli/330 |
Reference implementations of the GIMLI permutation |
| 12 |
5 |
1 |
2 years ago |
capi-streaming-framework/331 |
AFU framework for streaming applications with CAPI. |
| 12 |
3 |
0 |
1 year, 8 months ago |
Pixblasters-MicroDemo/332 |
Create video LED displays by RGB LED strips |
| 12 |
19 |
17 |
a month ago |
ipbus-firmware/333 |
Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol |
| 12 |
10 |
0 |
1 year, 2 months ago |
Basys-3-GPIO/334 |
None |
| 12 |
1 |
6 |
2 days ago |
karabas-pro/335 |
FPGA based retrocomputer with FDD and HDD controllers |
| 12 |
0 |
0 |
1 year, 11 days ago |
ArtyS7/336 |
Where Arty S7 projects are kept. MIT License unless file headers state otherwise. |
| 12 |
2 |
0 |
a month ago |
libvhdl/337 |
Library of reusable VHDL components |
| 12 |
2 |
0 |
2 years ago |
vm2413/338 |
A YM2413 clone module written in VHDL. |
| 12 |
12 |
0 |
4 years ago |
miilink/339 |
Connecting FPGA and MCU using Ethernet RMII |
| 11 |
9 |
0 |
8 years ago |
VHDL-Mips-Pipeline-Microprocessor/340 |
VHDL-Mips-Pipeline-Microprocessor |
| 11 |
4 |
0 |
6 years ago |
multicomp/341 |
Simple custom computer on a FPGA |
| 11 |
2 |
0 |
1 year, 3 months ago |
deocmpldcv/342 |
This project is a port of the 1chipMSX to DEOCM + DE0-CV including modification of OCM-PLD. |
| 11 |
6 |
1 |
4 years ago |
ArtyEtherentTX/343 |
Sending raw data from the Digilent Arty FPGA board |
| 11 |
4 |
0 |
2 months ago |
VCS-1/344 |
VCS-1 system |
| 11 |
4 |
0 |
1 year, 3 months ago |
REAPR/345 |
REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications such as regular expressions. REAPR is currently only compatible with SDAccel-capable Xilinx FPGA boards. |
| 11 |
12 |
0 |
4 years ago |
team_psx/346 |
18545 Repo |
| 11 |
1 |
0 |
12 days ago |
ZXNext_Mister/347 |
ZX Next core for Mister |
| 11 |
13 |
15 |
5 days ago |
bel_projects/348 |
GSI Timing Gateware and Tools |
| 11 |
1 |
0 |
6 years ago |
vsim/349 |
VHDL simulator in Haskell |
| 11 |
2 |
8 |
11 months ago |
Arcade-DonkeyKongJunior_MiSTer/350 |
Donkey Kong Junior arcade clone for MiSTer. |
| 11 |
12 |
1 |
3 years ago |
Arty-Z7-old/351 |
Board repository for the Arty Z7 |
| 11 |
1 |
0 |
15 hours ago |
Retro-Computers/352 |
Retro-Computer Designs (Z80, 65C816, etc) |
| 11 |
7 |
0 |
2 years ago |
EM070_New-FPGA-family-for-CNN-architectures-High-Speed-Soft-Neuron-Design/353 |
Who doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventional DSP and multiplier blocks? The optimized hard neuron design will allow all the software and hardware designers to create or test different deep learning network architectures, especially the convolutional neural networks (CNN), more easily and faster in comparing to any previous FPGA family in the market nowadays. The revolutionary idea about this project is to open the gate of creativity for a precise-tailored new generation of FPGA families that can solve the problems of wasting logic resources and/or unneeded buses width as in the conventional DSP blocks nowadays. The project focusing on the anchor point of the any deep learning architecture, which is to design an optimized high-speed neuron block which should replace the conventional DSP blocks to avoid the drawbacks that designers face while trying to fit the CNN architecture design to it. The design of the proposed neuron also takes the parallelism operation concept as it’s primary keystone, beside the minimization of logic elements usage to construct the proposed neuron cell. The targeted neuron design resource usage is not to exceeds 500 ALM and the expected maximum operating frequency of 834.03 MHz for each neuron. In this project, ultra-fast, adaptive, and parallel modules are designed as soft blocks using VHDL code such as parallel Multipliers-Accumulators (MACs), RELU activation function that will contribute to open a new horizon for all the FPGA designers to build their own Convolutional Neural Networks (CNN). We couldn’t stop imagining INTEL ALTERA to lead the market by converting the proposed designed CNN block and to be a part of their new FPGA architecture fabrics in a separated new Logic Family so soon. The users of such proposed CNN blocks will be amazed from the high-speed operation per seconds that it can provide to them while they are trying to design their own CNN architectures. For instance, and according to the first coding trial, the initial speed of just one MAC unit can reach 3.5 Giga Operations per Second (GOPS) and has the ability to multiply up to 4 different inputs beside a common weight value, which will lead to a revolution in the FPGA capabilities for adopting the era of deep learning algorithms especially if we take in our consideration that also the blocks can work in parallel mode which can lead to increasing the data throughput of the proposed project to about 16 Tera Operations per Second (TOPS). Finally, we believe that this proposed CNN block for FPGA is just the first step that will leave no areas for competitions with the conventional CPUs and GPUs due to the massive speed that it can provide and its flexible scalability that it can be achieved from the parallelism concept of operation of such FPGA-based CNN blocks. |
| 11 |
5 |
7 |
10 months ago |
fpgasdr/354 |
FPGA firmware for FPGA radio baseband board. Scroll down for README. |
| 11 |
6 |
0 |
2 years ago |
S2NN-HLS/355 |
Spiking neural network for Zynq devices with Vivado HLS |
| 11 |
9 |
0 |
6 years ago |
VHDL-Pong/356 |
Straightforward Pong Game written in VHDL. Scoring and Multiplayer |
| 11 |
6 |
0 |
28 days ago |
vhdl-hdmi-out/357 |
HDMI Out VHDL code for 7-series Xilinx FPGAs |
| 11 |
1 |
0 |
8 years ago |
DCPU16-VHDL/358 |
An implementation of the DCPU-16 from 0x10c in VHDL. |
| 11 |
0 |
0 |
2 years ago |
k1208-cpld/359 |
K1208 A1200 fastmem board CPLD logic |
| 11 |
1 |
1 |
3 months ago |
second_order_sigma_delta_DAC/360 |
A comparison of 1st and 2nd order sigma delta DAC for FPGA |
| 11 |
6 |
0 |
4 years ago |
fpga_fibre_scan/361 |
本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互，CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程： 1. 链路初始化： 在上位机完成USB固件的下载，并读取固件的信息状态描述后，通过上电复位或者手动复位，通过串口发送0X55给上位机，表明链路打通，一次握手成功。 2. 超声波发射与AD数据接收：在收到上位机通过串口发送的0X02指令后，开启（START），发送超声方波信号，（注：该START信号在处理过程被改变成包络信号）因为只是单阵元，所以就没有接收延迟聚焦的问题，但有皮肤表皮的客观实际和单阵元回波的时间消耗，所以在等到C_CORDIC_DELAY（1000）后，才开始AD数据的采集。（注：具体多少厚度，需要细算）。每次采集4096个数据，形成一个扫描线；总共需要采集300根扫描线，若不够，则需重新发送方波，并接收AD数据。 3. 剪切波发送： 在采集到第33根扫描线后，开始剪切波的发送，简单的发送50HZ的单载波就可以，此后的AD数据就含有剪切波的信息。 4. 控制通路的信息： 这里通过CYUSB3.0的串口来传送上位机发送的控制端口信息 ，包括数据通路的读和写指令（注：这里只需要通过BULK读取数据通路的数据，不需要通过BULK向数据通路写数据）；通过CYUSB3.0的串口来传送下位机FPGA的状态信息指令给上位机。（由于采用的是URAT，所以有FIFO缓存和数据发送接收状态控制操作） 5. 数据通路的信息： 这里通过上位机的读写指令来将数据存储到FIFO中，这里默认发送的是0X00指令，一直读取AD采集到的数据。并且采用的是BULK的Xfer->read的同步传输，一直要等到指定数目数据（4096*300）采集完才结束采集。 2.2.2 USB3.0模块 1. 这里首先要进行存储划分和寄存器映射，一般汇编或者其他CMD格式，然后编写BOOTLOAD汇编，最后中断跳转处理（汇编）。 2. 这里主要配置GPIF的异步串口参数和读写操作。 3. 这里需要给出CTL端口和BULK端口的配置和读写。 2.3 上位机软件 这里主要完成算法的处理和界面的显示和控制。 关于算法部分需要后面补充，目前没有完全消化。 处理流程： 1. 初始化USB，然后上位机通过控制端点发送写命令控制字（不加帧头命令）下位机未处理，开启监视工作线程循环，主要内容是：通过控制端点发送读命令控制字，通过控制端点读回串口信息，用来验证设备是否启动握手成功（0X55）。 2. 启动成功后引发响应的启动触发方法。启动触发方法中，先要延时大于0.36s，如果选中check_box，则使用存储的测试数据，若未选中，通过控制端点发送写start命令，开启bulk端口读循环线程，最后每次测量发送一次读bulk数据消息到消息队列。 3. 在bulk端口读循环线程中引发响应的bulk读方法，在bulk读方法中，主要调用底层的USB3.0的bulkin读方法，数据读上来后，post一个getData消息，交由绑定的函数来处理数据。 4. 数据处理包括二独立部分，一部分是原始数据产生MotionMOdel信息 ,一部分是原始数据产生剪切波速度和杨氏模量信息。 |
| 11 |
1 |
0 |
1 year, 2 months ago |
antDev/362 |
Agile Network Tester with FPGA & multi-cores |
| 11 |
2 |
2 |
2 years ago |
reVISION-Zybo-Z7-20/363 |
None |
| 11 |
2 |
0 |
9 years ago |
cpu_arm/364 |
An ARMv4 compatible CPU core. (INCOMPLETE) |
| 11 |
7 |
0 |
5 years ago |
VGA/365 |
VGA Tutorial for DE1 |
| 11 |
0 |
1 |
2 years ago |
mips-cpu/366 |
None |
| 11 |
1 |
0 |
11 months ago |
synthowheel/367 |
Polyphonic additive wheeltone synthesizer core |
| 11 |
7 |
0 |
5 years ago |
miniOV7670/368 |
Interfacing OV7670 Camera module to miniSpartan6+ |
| 11 |
3 |
0 |
1 year, 9 months ago |
ZYNQ-PYNQ-Z2-Gobang/369 |
参加2018第二届全国大学生FPGA创新设计邀请赛的作品 |
| 11 |
0 |
0 |
6 years ago |
xentral/370 |
XENTRAL is a simple Harvard Architecture CPU. |
| 11 |
5 |
0 |
a month ago |
getting-started-FV/371 |
None |
| 11 |
30 |
2 |
1 year, 18 days ago |
2018_FPGA_Design/372 |
FPGA Design lab |
| 11 |
1 |
0 |
2 years ago |
AnalogCPU/373 |
8位模型机（数字电子课程设计） |
| 11 |
9 |
1 |
12 days ago |
OpenHT/374 |
Hybrid Threading Tool Set |
| 11 |
2 |
0 |
1 year, 10 months ago |
Xilinx-Deep-Learning-Nexys4/375 |
Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK |
| 11 |
6 |
0 |
7 months ago |
Digital-Hardware-Modelling/376 |
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL) |
| 11 |
8 |
1 |
6 years ago |
SpaceWireCODECIP_100MHz/377 |
None |
| 10 |
3 |
0 |
11 years ago |
Pong/378 |
Pong for Spartan3 FPGA-Board written in VHDL |
| 10 |
5 |
3 |
4 months ago |
TI-99_4A_MiSTer/379 |
Texas Instrument 99/4A Home Computer |
| 10 |
7 |
0 |
15 days ago |
MiSTer_DB9/380 |
Unofficial cores with DB9 support |
| 10 |
2 |
0 |
3 years ago |
MIPS/381 |
VHDL implementation of a MIPS processor for Spartan-6 FPGA |
| 10 |
0 |
0 |
6 months ago |
16x16-bit-Dada-multiplication/382 |
Design a Dadda multiplier for unsigned 16x16 bit multiplication with a Brent Kung adder for the final addition in synthesizable VHDL. |
| 10 |
22 |
1 |
4 years ago |
hostmot2-firmware/383 |
HostMot2 FPGA firmware |
| 10 |
1 |
0 |
5 months ago |
hardware-sort/384 |
Hardware-accelerated sorting algorithm |
| 10 |
2 |
0 |
1 year, 7 months ago |
ultra96_design/385 |
Repository of HW design and SW for Ultra96 board + MIPI board |
| 10 |
16 |
0 |
7 years ago |
LEON2/386 |
LEON2 SPARC CPU IP core LGPL by Gaisler Research |
| 10 |
2 |
0 |
1 year, 1 month ago |
VHDLBoy/387 |
VHDL Gameboy implementation |
| 10 |
7 |
0 |
4 years ago |
wireless-mac-processor/388 |
None |
| 10 |
4 |
0 |
1 year, 4 months ago |
s4noc/389 |
A Statically-scheduled TDM Network-on-Chip for Real-Time Systems |
| 10 |
0 |
0 |
6 months ago |
32-bit-Brent-Kung-architecture/390 |
Brent Kung architecture for adding 32 bit operands. |
| 10 |
3 |
2 |
4 years ago |
aes-fpga/391 |
AES implementation on FPGA |
| 10 |
4 |
1 |
1 year, 4 months ago |
Shouji/392 |
Shouji is fast and accurate pre-alignment filter for banded sequence alignment calculation. Described in the Bioinformatics journal paper (2019) by Alser et al. at https://academic.oup.com/bioinformatics/advance-article-pdf/doi/10.1093/bioinformatics/btz234/28533771/btz234.pdf |
| 10 |
4 |
1 |
6 years ago |
snes-flash/393 |
None |
| 10 |
5 |
0 |
4 days ago |
fpga_ip/394 |
OscillatorIMP ecosystem FPGA IP sources |
| 10 |
3 |
1 |
3 years ago |
tdc/395 |
A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA. |
| 10 |
12 |
0 |
8 months ago |
jpeg_open/396 |
A hardware MJPEG encoder and RTP transmitter |
| 10 |
3 |
0 |
Unknown |
Hi-DMM/397 |
Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis) |
| 10 |
0 |
2 |
Unknown |
AlteraMeatBoyHD/398 |
Quartus project files for an Altera DE2 Meat Boy game. Proper functionality not guaranteed. |
| 10 |
0 |
0 |
3 years ago |
IBM2030/399 |
An IBM System/360 Model 30 in VHDL |
| 10 |
2 |
1 |
Unknown |
UART/400 |
Simple UART implementation in VHDL |
| 10 |
3 |
1 |
Unknown |
LimeSDR_DVBSGateware/401 |
Optimised gateware for lime sdr mini |
| 10 |
1 |
0 |
1 year, 8 months ago |
prjtrellis-dvi/402 |
DVI video out example for prjtrellis |
| 10 |
6 |
0 |
7 months ago |
LMAC_CORE3/403 |
Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps |
| 10 |
1 |
0 |
13 days ago |
Homebrew-65C02-Computer/404 |
A homebrew 65C02 based computer with PS/2 Keyboard, Serial & Parallel IO + 3 Expansion slots |
| 10 |
0 |
9 |
Unknown |
vhdeps/405 |
VHDL dependency analyzer |
| 11 |
0 |
2 |
Unknown |
Papilio-Master-System/406 |
None |
| 10 |
4 |
0 |
Unknown |
GateKeeper/407 |
GateKeeper: Fast Alignment Filter for DNA Short Read Mapping |
| 10 |
8 |
0 |
Unknown |
fpga-camera/408 |
FPGA digital camera controller and frame capture device in VHDL |
| 10 |
2 |
1 |
Unknown |
vextproj/409 |
VEXTPROJ - the version control friendly system for creation of Vivado projects |
| 10 |
5 |
0 |
Unknown |
fpga-led-matrix/410 |
HDMI decoder and LED matrix controller on a Spartan-6 FPGA |
| 10 |
3 |
0 |
1 year, 3 months ago |
100cerebros/411 |
Resoluções de exercícios e guiões de diversas disciplinas de MIECT, na UA |
| 10 |
3 |
1 |
Unknown |
FPGA_Mandelbrot/412 |
A real-time Mandelbrot fractal viewer for FPGAs |
| 10 |
0 |
0 |
3 years ago |
SAYEH/413 |
SAYEH cpu-memory basic computer |
| 10 |
10 |
2 |
5 months ago |
Arcade-Galaga_MiSTer/414 |
Arcade: Galaga for MiSTer |
| 10 |
0 |
0 |
5 months ago |
UK101onFPGA/415 |
Fork of the emulator for Compukit UK101 on FPGA |
| 10 |
2 |
0 |
8 years ago |
MIPS/416 |
A pipelined MIPS processor written in VHDL (Unicamp/MC542) |
| 10 |
2 |
1 |
4 months ago |
agc_monitor/417 |
Modern implementation of the AGC Monitor, for use with a real Apollo Guidance Computer |
| 10 |
1 |
0 |
2 years ago |
8_bit_cpu/418 |
ALINX ALTERA FPGA黑金开发学习板 CYCLONE IV 数电课设八位模型机 |
| 10 |
5 |
0 |
4 years ago |
Zynq_Project/419 |
Zynq project to interface OV2640 camera module |
| 10 |
7 |
2 |
6 months ago |
Pynq-CV-OV5640/420 |
Pynq computer vision examples with an OV5640 camera |
| 9 |
2 |
2 |
1 year, 8 months ago |
pim-vhdl/421 |
My VHDL code |
| 9 |
1 |
0 |
2 months ago |
FPGA-SPI-Flash/422 |
Various projects of SPI loader module for xilinx fpga |
| 9 |
3 |
0 |
2 years ago |
Aeon-Lite/423 |
Aeon Lite - Open Source Reconfigurable Computer |
| 9 |
6 |
0 |
a month ago |
Accelerating-Quantized-CNN-Inference-on-FPGA/424 |
Accelerating-Quantized-CNN-Inference-on-FPGA(RTL) |
| 9 |
6 |
0 |
2 years ago |
pacedev/425 |
Programmable Arcade Circuit Emulation |
| 9 |
3 |
0 |
9 months ago |
j-core-ice40/426 |
J-core SOC for ice40 FPGA |
| 9 |
1 |
0 |
6 years ago |
PSP-Display-Driver/427 |
VHDL code for driving a playstation portable display |
| 9 |
6 |
0 |
2 years ago |
bce-fpga-dev-kit/428 |
bce-fpga-dev-kit |
| 9 |
2 |
0 |
8 years ago |
fpgasynth/429 |
VHDL for an FPGA based MIDI music synthesizer |
| 9 |
0 |
0 |
5 years ago |
macMonitor/430 |
Xilinx VHDL project to drive a Mac Classic CRT |
| 9 |
3 |
2 |
7 years ago |
vhdl-csv-file-reader/431 |
VHDL package for reading formatted data from comma-separated-values (CSV) files |
| 9 |
4 |
0 |
4 years ago |
RSA-Encryption/432 |
VHDL implementation of RSA encryption/decryption using Montgomery modular multipliers |
| 9 |
1 |
1 |
3 years ago |
argh2600/433 |
VHDL implementation of an Atari 2600 |
| 9 |
3 |
1 |
4 years ago |
6502/434 |
VHDL description of 6502 processor with FPGA synthesis support. |
| 9 |
1 |
0 |
5 years ago |
ZPUino_miniSpartn6_plus/435 |
ZPUino for miniSpartan6+ |
| 9 |
4 |
0 |
9 years ago |
coded_aperture_vhdl/436 |
vhdl code for simulating/synthesizing an FPGA backend of a coded aperture |
| 9 |
1 |
0 |
7 years ago |
fp68060/437 |
PCB to plug FPGA softcore CPU into 68060 microprocessor socket |
| 9 |
6 |
1 |
2 years ago |
Zybo-Z7-20-base-linux/438 |
None |
| 9 |
0 |
1 |
4 years ago |
vertcl/439 |
VHDL Tcl interpreter |
| 9 |
2 |
1 |
2 years ago |
FpgaMicrotubule/440 |
HPC Implementation of dynamic microtubules calculations on CPU, GPU and FPGA Platforms |
| 9 |
2 |
0 |
6 years ago |
gandalf-miner/441 |
bitcoin miner for the A3255-Q48 chip |
| 9 |
3 |
0 |
2 years ago |
BoostDSP/442 |
VHDL Library for implementing common DSP functionality. |
| 9 |
13 |
0 |
3 years ago |
SDSoC-platforms/443 |
SDSoC platforms for Digilent Zynq boards |
| 9 |
1 |
0 |
8 years ago |
fpga-midi-synth/444 |
MIDI synthesizer written in VHDL |
| 9 |
6 |
17 |
6 years ago |
ECE383/445 |
USAFA ECE383 course website. |
| 9 |
3 |
0 |
1 year, 4 months ago |
robotter/446 |
Rob'Otter's code for Eurobot and the Coupe de France de robotique |
| 9 |
8 |
1 |
6 years ago |
BeMicro-CV/447 |
A "hello world" style designs for the Cyclone V based $49 Arrow BeMicro CV |
| 9 |
1 |
0 |
9 months ago |
MiSTer-Arcade-AtariTetris/448 |
FPGA implementation of ATARI's Tetris arcade game |
| 9 |
4 |
0 |
1 year, 3 months ago |
cmips/449 |
All things related to cMIPS, a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core. |
| 9 |
1 |
0 |
a month ago |
LMAC_CORE1/450 |
LMAC Core1 - Ethernet 1G/100M/10M |
| 9 |
1 |
0 |
1 year, 1 month ago |
probe-scope-fpga/451 |
FPGA Software for the Probe-Scope |
| 9 |
3 |
0 |
3 years ago |
MQP/452 |
Electrical and Computer Engineering Capstone |
| 9 |
6 |
0 |
9 years ago |
image_processing_examples/453 |
Examples of image processing |
| 9 |
1 |
0 |
3 years ago |
bcomp/454 |
8-bit computer |
| 9 |
3 |
0 |
3 years ago |
2DImageProcessing/455 |
2d Images processing system with FPGA (Zynq 7k) from two dragster linescanner (DR-2k-7) |
| 9 |
4 |
0 |
4 years ago |
VGA_1.0/456 |
AXI memory-mapped VGA module originally designed for the Avent Zedboard |
| 9 |
4 |
0 |
8 years ago |
simple-mips/457 |
Simple MIPS processor written in VHDL |
| 9 |
3 |
1 |
2 years ago |
CPU-Adelie/458 |
None |
| 9 |
6 |
1 |
2 months ago |
psi_common/459 |
Common elements for FPGA Design (FIFOs, RAMs, etc.) |
| 9 |
8 |
0 |
3 years ago |
aes-over-pcie/460 |
A VHDL implementation of 128 bit AES encryption with a PCIe interface. |
| 9 |
5 |
0 |
3 months ago |
cpu86/461 |
CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA |
| 9 |
0 |
0 |
a month ago |
formal_hw_verification/462 |
Trying to verify Verilog/VHDL designs with formal methods and tools |
| 9 |
2 |
0 |
3 years ago |
msgpack-vhdl/463 |
MessagePack implementation for VHDL |
| 8 |
8 |
5 |
3 months ago |
VIC20_MiSTer/464 |
Commodore VIC-20 for MiSTer |
| 8 |
5 |
1 |
2 years ago |
Nexys-4-DDR-GPIO/465 |
None |
| 8 |
4 |
2 |
8 years ago |
ethernet_mac/466 |
A VHDL implementation of an Ethernet MAC |
| 8 |
4 |
0 |
2 months ago |
cryptocores/467 |
cryptography ip-cores in vhdl / verilog |
| 8 |
2 |
0 |
4 years ago |
FPGA_Flappy_Bird/468 |
🐦 a simple hardware-implementation of the viral game "Flappy Bird" built for use on the Digilent NEXYS 2 Development Board (XC3S500E-FG320) |
| 8 |
5 |
1 |
2 years ago |
aws-fpga-miner/469 |
None |
| 8 |
0 |
0 |
9 months ago |
chisel-study/470 |
ハードウェア構築言語Chiselでちょっとしたコードを書き溜めておくプロジェクト |
| 8 |
1 |
0 |
1 year, 2 months ago |
RISC-CPU/471 |
A multi cycle RISC CPU (processor) like MIPS CPU in VHDL ( a hardware side code implementation ) |
| 8 |
8 |
0 |
5 years ago |
HLS-Axi-Master-on-Microzed-with-Yocto-Linux-device-driver/472 |
Creation of a AXI Master and Yocto device driver for Zynq, using High Level Synthesis (HLS) techniques. |
| 8 |
3 |
0 |
3 years ago |
mdsynth/473 |
FPGA-based synthesizer in VHDL for the Xilinx Spartan-3A and Spartan-3E Starter Kits |
| 8 |
2 |
0 |
3 years ago |
tetris-vhdl/474 |
A bare-metal pure hardware implementation of the Tetris game for FPGA |
| 8 |
2 |
0 |
4 months ago |
360-NAND-X/475 |
Clone of the NAND-X |
| 8 |
0 |
0 |
8 months ago |
cod19grp4/476 |
奋战一学期 造台联网计算机（CPU+硬件路由器） |
| 8 |
1 |
2 |
5 years ago |
oram_fpga/477 |
FPGA related files for ORAM |
| 8 |
5 |
0 |
1 year, 10 months ago |
Arty-A7-35-GPIO/478 |
None |
| 8 |
2 |
0 |
3 years ago |
ImageCaptureSystem/479 |
A Xilinx IP Core and App for line scanner image capture and store |
| 8 |
4 |
0 |
2 years ago |
srio_test/480 |
Test SRIO connection between FPGA (Kintex-7) and DSP (C6678) |
| 8 |
1 |
0 |
5 years ago |
siphash/481 |
A VHDL implementation of SipHash |
| 8 |
2 |
0 |
4 years ago |
SNN_vhdl/482 |
Implementation of an Artificial Neural Network (ANN) on FPGA using VHDL |
| 8 |
0 |
1 |
7 months ago |
posit_blas_hdl/483 |
Posit Arithmetic Accelerator interfacing with Apache Arrow & CAPI SNAP |
| 8 |
0 |
0 |
9 months ago |
tangnano_sample/484 |
Tang-nano LCD sample |
| 8 |
1 |
0 |
7 years ago |
sdr/485 |
A software-defined radio. |
| 8 |
1 |
0 |
2 years ago |
vu_meter/486 |
FPGA-based FFT audio spectrum analyzer |
| 8 |
2 |
0 |
2 years ago |
Arty-Pmod-VGA/487 |
None |
| 8 |
5 |
0 |
8 years ago |
soc_leon3/488 |
System on Chip SPARC V8 using leon3 CPU by Gaisler. C++, vhdl, v files. |
| 8 |
0 |
0 |
2 years ago |
zlogan/489 |
High-througput logic analyzer for FPGA |
| 8 |
12 |
7 |
5 months ago |
Arcade-Galaxian_MiSTer/490 |
Arcade: Galaxian for MiSTer |
| 8 |
0 |
0 |
1 year, 4 months ago |
PingPongGame_CAD_VGA/491 |
🏓 A Ping Pong game written in VHDL with VGA support |
| 8 |
8 |
0 |
4 years ago |
zycap/492 |
Zynq PR Management |
| 8 |
1 |
5 |
1 year, 11 months ago |
cpu/493 |
MIPS CPU |
| 8 |
5 |
0 |
5 years ago |
FIRFilter/494 |
This project is a High and Low pass filter designer written in Octave to design and calculate the filter coefficients for a windows sinc filter. The coefficients can be used in the vhdl code for signal processing. |
| 8 |
0 |
4 |
5 years ago |
tis100cpu/495 |
TIS-100 CPU in VHDL |
| 8 |
5 |
0 |
2 years ago |
Sha256_Hw_Accelerator/496 |
SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent |
| 8 |
3 |
20 |
19 days ago |
ZXInterfaceZ/497 |
ZX Spectrum InterfaceZ |
| 8 |
4 |
1 |
2 hours ago |
dsd/498 |
Digital System Design |
| 8 |
6 |
0 |
3 years ago |
GBA/499 |
GameBoy Advance Zedboard Implementation |
| 8 |
2 |
0 |
5 years ago |
hls_stream/500 |
Xilinx HLS video library using hls::stream w/ Vivado 2014.4 or Later |
| 8 |
15 |
0 |
7 years ago |
VinxFs/501 |
Small FAT16/FAT32 filesystem for ATMega8 (AVR / STM / PIC) with create/delete file |
| 8 |
2 |
0 |
6 years ago |
zpu-lattice/502 |
ZPU Core for Lattice ICE40HX8K |
| 8 |
0 |
0 |
5 months ago |
VHDL6526/503 |
None |
| 8 |
16 |
0 |
6 years ago |
AD/504 |
Altium Desinger |
| 8 |
1 |
0 |
2 years ago |
VIIRF/505 |
Hardware description (VHDL) and configuration scripts (Python) of a versatile IIR Filter implemented as cascaded SOS/biquads. No vendor-specific hardware constructs used. |
| 8 |
10 |
0 |
4 years ago |
zybo_petalinux/506 |
Small projects intended to run on the Digilent Zybo development board, utilizing PetaLinux on the Zynq's ARM processor. |
| 8 |
1 |
0 |
9 months ago |
Nexys4DDR-ARM-M3-Plate-Recognition/507 |
车牌识别,FPGA,2019全国大学生集成电路创新创业大赛 |
| 8 |
1 |
0 |
7 years ago |
Mandelbrot-VHDL/508 |
Mandelbrot Set in VHDL targetting the Cyclone IVE found on a DE2-115 board. |
| 8 |
2 |
0 |
1 year, 5 months ago |
RealTimeVideo/509 |
High-speed real time streaming video on Zybo Z7-10 |
| 8 |
0 |
0 |
2 years ago |
courses/510 |
About university courses and homeworks ... |
| 8 |
6 |
1 |
5 years ago |
OLED_on_ZedBoard/511 |
OLED test code from Digilink modified to work on the Zedboard |
| 8 |
5 |
0 |
2 years ago |
FPGA-shared-mem/512 |
Exploring Shared Virtual Memory Abstractions in OpenCL Tools for FPGAs |
| 8 |
0 |
0 |
2 years ago |
VHDLMatrixMultiplier/513 |
VHDL implementation for a Matrix Multiplier |
| 8 |
5 |
0 |
4 years ago |
kvcordic/514 |
Multi-function, universal, fixed-point CORDIC |
| 8 |
5 |
0 |
3 years ago |
VHDL/515 |
Some VHDL code |
| 8 |
2 |
3 |
4 months ago |
SAMCoupe_MIST/516 |
SAM Coupe for MiST board |
| 8 |
0 |
0 |
3 months ago |
Multi-TB-progetto-Reti/517 |
Tb per la prova finale del corso di Reti del Politecnico di Milano. |
| 8 |
8 |
0 |
2 years ago |
SRAI_HW_ACCEL_WINDOWS10_PCIe/518 |
PCIe based accelerator for VCU1525 with xDMA based on Windows10 and Windows Server 2016 development environment |
| 8 |
1 |
0 |
10 months ago |
naiverouter/519 |
A router IP written in Verilog. |
| 8 |
8 |
0 |
9 years ago |
udp_ip__core/520 |
UDP/IP Core |
| 8 |
4 |
0 |
5 years ago |
NfcEmu/521 |
SDR/FPGA-based NFC/RFID Emulator |
| 8 |
7 |
0 |
6 years ago |
aeshw/522 |
None |
| 8 |
6 |
0 |
3 years ago |
16-bit-HDLC-using-VHDL/523 |
High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language. |
| 8 |
3 |
1 |
2 years ago |
MultiComp_MiSTer/524 |
Port of Grant Searle's MultiComp to the MiSTer |
| 8 |
1 |
0 |
23 days ago |
FPGA-X68k-DE0CV/525 |
None |
| 7 |
2 |
0 |
1 year, 2 months ago |
NexysPsram/526 |
AXI PSRAM Controller IP for use with Digilent Nexys 4 |
| 7 |
0 |
0 |
9 years ago |
Brainfuck-Processor/527 |
A simple brainfuck processor implemented in VHDL. |
| 7 |
0 |
1 |
9 months ago |
metamachine/528 |
Experimental CPU with software-defined instruction set. |
| 7 |
4 |
0 |
14 years ago |
ofdm/529 |
OFDM modem |
| 7 |
4 |
0 |
1 year, 3 months ago |
Circuitos_Reconfiguraveis/530 |
Repositório da disciplina de Projeto com Circuitos Reconfiguráveis do curso de Engenharia Eletrônica da Faculdade UnB Gama. |
| 7 |
0 |
0 |
6 years ago |
i2s-interface-vhdl/531 |
A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface. |
| 7 |
6 |
0 |
4 months ago |
jcore-cpu/532 |
J-Core J2/J32 5 stage pipeline CPU core |
| 8 |
4 |
0 |
a month ago |
Getting-to-Know-Vivado/533 |
Source files for Getting to Know Vivado course |
| 7 |
0 |
0 |
5 years ago |
TicksPicker/534 |
Tiny VHDL postbit length extractor |
| 7 |
10 |
1 |
3 years ago |
OFDM_Synchronization/535 |
Design a new OFDM synchronization algorithm, and implement it with both Matlab and Verilog. |
| 7 |
0 |
0 |
1 year, 4 months ago |
Computer-Organization-and-Architecture-Course-Design/536 |
这是东南大学信息学院本科三年级开设的计算机组织与结构课程的后续配套实验课程，包含POC设计和简单CPU设计。以下是我与小组完成的POC与CPU的设计，采用vivado2018.2的设计环境。 |
| 7 |
4 |
1 |
1 year, 6 months ago |
Space-Invaders-for-MiSTer/537 |
None |
| 7 |
1 |
0 |
a month ago |
tiny_z80/538 |
Business Card Sized Z80 Single Board Computer |
| 7 |
4 |
0 |
6 years ago |
FPGA_ADC/539 |
Interface the AD9057 with a cyclone III FPGA |
| 7 |
1 |
0 |
3 years ago |
SimpleComputer/540 |
The design and implementation of simple computer by quartus. |
| 7 |
0 |
0 |
1 year, 10 months ago |
Connect4VHDL/541 |
Spartan3 implementation of the popular game Connect 4 written in VHDL |
| 7 |
2 |
0 |
6 years ago |
vhdl-game-engine/542 |
A game engine implemented purely in hardware using the VHDL language |
| 7 |
1 |
0 |
3 years ago |
16x2-LCD-Controller-VHDL/543 |
A little program I wrote to control the LCD on my FPGA |
| 7 |
7 |
0 |
4 years ago |
fpga/544 |
None |
| 7 |
2 |
0 |
1 year, 6 months ago |
vgg16-on-Zynq/545 |
Simulating implement of vgg16 network on Zynq-7020 FPGA |
| 7 |
3 |
0 |
5 years ago |
Stepper-Motor-Control/546 |
System on a Chip - Design for a stepper-motor-control with NIOS II/s µC on Cyclone IV/V FPGA |
| 7 |
6 |
0 |
5 years ago |
SHA3-VHDL/547 |
Hardware implementation of cryptographic Hash function SHA-3 (keccak) using VHDL |
| 7 |
0 |
0 |
3 years ago |
UART_in_VHDL/548 |
My successful first experiment in VHDL - creating my own UART |
| 7 |
0 |
0 |
1 year, 8 days ago |
seqpu/549 |
A bit-serial CPU |
| 7 |
4 |
1 |
3 years ago |
Nexys-4-OOB/550 |
None |
| 7 |
4 |
0 |
2 years ago |
SECURE_HASH/551 |
SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera). |
| 7 |
4 |
0 |
4 years ago |
ece5775-final/552 |
Voice Recognition using FPGA-Based Neural Networks |
| 7 |
5 |
5 |
2 months ago |
dsp-cores/553 |
Repository containing the DSP gateware cores |
| 7 |
1 |
0 |
8 months ago |
snes_cic_fpga/554 |
snes cic implementation with FPGA FireAnt board |
| 7 |
0 |
0 |
5 months ago |
ImpeccableCircuits/555 |
Hardware designs for fault detection |
| 7 |
0 |
1 |
5 months ago |
big80/556 |
FPGA Implementation of a TRS-80 Model 1 |
| 7 |
3 |
0 |
7 years ago |
FIX/557 |
FIX for (High Frequency Trading) HFT |
| 7 |
0 |
1 |
1 year, 10 months ago |
fpga_mpu401/558 |
MPU-401 Implementation on FPGA. Based on the System68 CPU core by John E. Kent. |
| 7 |
10 |
1 |
1 year, 4 months ago |
cnn-fpga-rtl/559 |
The CNN architecture elements implemented with RTL approach in VHDL. |
| 7 |
7 |
0 |
1 year, 1 month ago |
SidewinderFPGA/560 |
Sidewinder FPGA |
| 7 |
1 |
0 |
2 years ago |
Team-SDK-545/561 |
An FPGA design project by Kais Kudrolli, Sohil Shah, and DongJoon Park for 18-545 at Carnegie Mellon University. |
| 7 |
0 |
0 |
1 year, 1 month ago |
PIC16C6XX/562 |
Original Xbox SMC Power Glitching Attack (WIP) |
| 7 |
5 |
3 |
3 years ago |
Zybo-hdmi-in/563 |
None |
| 7 |
4 |
0 |
2 months ago |
Amstrad_MiST/564 |
None |
| 7 |
1 |
0 |
a month ago |
zxuno/565 |
None |
| 7 |
4 |
2 |
9 days ago |
Arcade-Tecmo_MiSTer/566 |
MiSTer arcade core for Tecmo arcade classics: Rygar (1986), Gemini Wing (1987), and Silkworm (1988). |
| 7 |
6 |
0 |
5 years ago |
montecarlo-fpga/567 |
Black-Scholes style options pricing using Monte Carlo methods. Written in VHDL for the Cyclone IV FPGA board. |
| 7 |
6 |
0 |
8 years ago |
grlib/568 |
None |
| 7 |
3 |
0 |
3 years ago |
uCPUvhdl/569 |
An 8-bit soft processor in VHDL |
| 7 |
4 |
0 |
1 year, 6 months ago |
LeNet-on-Zynq/570 |
Simulating implement of LeNet network on Zynq-7020 FPGA |
| 7 |
1 |
0 |
5 years ago |
PothosFPGA/571 |
Pothos FPGA computational offload and buffer integration support |
| 7 |
3 |
0 |
4 years ago |
FPGA-LCD-Driver/572 |
FPGA LVDS LCD driver |
| 7 |
4 |
2 |
3 years ago |
C64_MIST/573 |
None |
| 7 |
3 |
0 |
5 years ago |
rdsfpga/574 |
RDS FM modulator for FPGA |
| 7 |
3 |
0 |
2 years ago |
VGA_mem_mapped/575 |
Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it. |
| 7 |
4 |
2 |
5 years ago |
riffa/576 |
RIFFA (Reusable Integration Framework for FPGA Accelerators) is a framework developed in University of California, San Diego. This project utilises the RIFFA framework to define an interface to interact with a user's IP core on the FPGA to send and receive data to and from the PC. This particular project is being developed under Imperial College London. |
| 7 |
0 |
0 |
5 years ago |
AM2901/577 |
None |
| 7 |
0 |
0 |
1 year, 11 months ago |
OscilloscopeBoom/578 |
Display something on an analog oscilloscope |
| 7 |
6 |
0 |
6 years ago |
Xilinx-GPIO-Interrupt/579 |
It is a GPIO interrupt example for xilinx ZYNQ FPGA. |
| 7 |
2 |
0 |
2 years ago |
fpga_fifo/580 |
Asynchronous FIFO for FPGAs |
| 7 |
3 |
0 |
1 year, 10 months ago |
FpChip8/581 |
FPGA implementation of CHIP-8 using VHDL. |
| 7 |
5 |
0 |
6 years ago |
mbc5-clone/582 |
this is a clone of zakos mbcx found at https://gitorious.org/mbcx/mbcx. I'll try to make my own itteration of the mbcx. |
| 7 |
6 |
0 |
5 years ago |
Cameralink-LPC-FMC-Module/583 |
None |
| 7 |
2 |
0 |
30 days ago |
fpga_cores/584 |
None |
| 7 |
0 |
1 |
4 months ago |
Brutzelkarte_FPGA/585 |
The Brutzelkarte FPGA description code in VHDL |
| 7 |
16 |
0 |
8 days ago |
riscv-multicycle/586 |
None |
| 7 |
1 |
5 |
3 years ago |
ProjectZ/587 |
Attempt to implement MultiLayer Perceptron in hardware descriptive language like VHDL. |
| 7 |
1 |
0 |
2 years ago |
MIST_C64/588 |
FPGA implementation of a Commodore 64 |
| 7 |
1 |
2 |
5 months ago |
SharpMZ_MiSTer/589 |
Sharp MZ Series Personal/Business Computer Emulator for FPGA |
| 7 |
0 |
0 |
7 years ago |
rekonstrukt/590 |
FPGA based Forth development environment / Forth based FPGA development environment |
| 7 |
3 |
0 |
11 months ago |
VHDL-CPU/591 |
Simple CPU written in VHDL. |
| 7 |
2 |
7 |
2 months ago |
R32V2020/592 |
32-bit RISC for smallish FPGAs |
| 7 |
0 |
0 |
3 years ago |
patmos_HLS/593 |
Hardware Accelerators (HwAs) constructed in Vivado HLS |
| 7 |
1 |
0 |
4 years ago |
scanline-stereo-vision-FPGA/594 |
Implementazione VHDL dell’algoritmo Scanline |
| 8 |
2 |
0 |
3 years ago |
absenc/595 |
Absolute encoder VHDL core |
| 7 |
2 |
0 |
2 years ago |
Bitmap-VHDL-Package/596 |
A vhdl package for reading and writing bitmap files. |
| 7 |
4 |
0 |
1 year, 1 month ago |
FISC-VHDL/597 |
FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64 |
| 7 |
2 |
0 |
a month ago |
hdl_string_format/598 |
VHDL package to provide C-like string formatting |
| 7 |
8 |
2 |
6 years ago |
VHDL-Project-16-bit-RISC-Processor/599 |
Designed a RISC processor with 16 bit instruction set, 4-stage pipeline and a non-pre-emptive interrupt handler. Implemented it in VHDL and tested it by simulating in ModelSim. |
| 7 |
2 |
0 |
1 year, 14 days ago |
udp_ip_stack/600 |
UDP IP stack example project from this VUnit getting started blog (https://www.linkedin.com/pulse/vunit-best-value-initial-effort-lars-asplund) |
| 7 |
1 |
0 |
3 years ago |
FPGADisplay-ipcore/601 |
FPGA VGA Display Handler - IP Core Repository |
| 7 |
1 |
0 |
4 years ago |
MT32_Rand_Gen/602 |
Mersenne Twister Pseudo Random Number Generator written in VHDL(RTL) for FPGA(Xilinx and Altera). |
| 7 |
7 |
2 |
3 years ago |
go2uvm/603 |
Main repo for Go2UVM source code, examples and apps |
| 7 |
0 |
0 |
4 years ago |
65816_Interface_System/604 |
Soft Core of 65816 in VHDL |
| 7 |
6 |
0 |
4 years ago |
wavelet-image-compression/605 |
Simple FPGA-based Wavelet Image Compression |
| 7 |
4 |
0 |
4 years ago |
vhdl2008c/606 |
VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl |
| 7 |
0 |
1 |
1 year, 9 months ago |
pipemania-fpga-game/607 |
Pipe Mania - Game for FPGA written in VHDL |
| 7 |
1 |
0 |
2 years ago |
Ultrasound-Beamforming-/608 |
This project is basically ultrasound Beamformer prototype and FPGA is used to control all the modules of the Hardware. |
| 7 |
0 |
0 |
4 years ago |
2D-Image-Filtering-on-FPGA/609 |
None |
| 7 |
4 |
2 |
4 months ago |
cnn_vhdl_generator/610 |
AUTOMATIC VHDL GENERATION FOR CNN MODELS |
| 8 |
0 |
1 |
5 months ago |
FPGA-OV2640/611 |
This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA. |
| 7 |
3 |
0 |
1 year, 9 months ago |
AD9361_TX_GMSK/612 |
A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK |
| 7 |
7 |
1 |
5 months ago |
capi2-bsp/613 |
CAPI 2.0 Board Support Package |
| 7 |
1 |
0 |
3 years ago |
Mandelbrot-Explorer/614 |
An FPGA-based Mandelbrot Set explorer using the Papilio Duo board from Gadget Factory. |
| 7 |
4 |
0 |
4 years ago |
vhdI2CMaster/615 |
I2C Master FSM (vhdl) |
| 7 |
1 |
0 |
1 year, 4 months ago |
MIPS_Single_Cycle_CPU/616 |
MIPS Single Cycle CPU |
| 7 |
2 |
7 |
9 months ago |
Compliance-Tests/617 |
None |
| 7 |
2 |
0 |
2 months ago |
Async-Click-Library/618 |
None |
| 7 |
20 |
25 |
a month ago |
DeSCAM/619 |
DESCAM enables a new top-down hardwa design flow |
| 6 |
2 |
0 |
3 years ago |
ECE368-Lab/620 |
ECE368 |
| 6 |
1 |
0 |
3 years ago |
SHA-256-HDL/621 |
An implementation of original SHA-256 hash function in (RTL) VHDL |
| 6 |
1 |
0 |
3 years ago |
USTC-tMIPS/622 |
None |
| 6 |
0 |
0 |
3 years ago |
ov7670_zybo/623 |
None |
| 6 |
1 |
0 |
7 months ago |
can-lite-vhdl/624 |
A lightweight Controller Area Network (CAN) controller in VHDL |
| 6 |
2 |
0 |
2 months ago |
pipelineCPU/625 |
Five-Stage Pipeline CPU Implemented by Verilog on FPGA Written By LI Shuai, it supports static and dynamic pipeline cpu. I am not maintaining this repo for years. If there are bugs when you try it, debug by youself! 😃 |
| 6 |
3 |
1 |
4 months ago |
ps2_cpld_kbd/626 |
ZX Spectrum PS/2 keyboard adapter |
| 6 |
2 |
0 |
2 years ago |
I2S_sender/627 |
VHDL I2S transmitter |
| 6 |
1 |
0 |
1 year, 1 month ago |
Zynq_HLS_DDR_Dataflow_kernel_2mm/628 |
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation |
| 6 |
8 |
2 |
5 years ago |
bluedbm_connectald/629 |
BlueDBM |
| 6 |
1 |
0 |
4 years ago |
vhdl_sincos_gen/630 |
Sine / cosine function core in VHDL |
| 6 |
2 |
0 |
3 years ago |
axi_stream_master/631 |
Source files for AXI Stream tutorial |
| 6 |
0 |
0 |
2 years ago |
adc_configurator/632 |
ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on) |
| 6 |
0 |
0 |
1 year, 5 months ago |
4Bit-Calculator/633 |
A bit calculator, implemented in VDHL that provides 4 bits sum, subtraction, inversion, major and minor verification. The result is shown in a 7 segment display on a FPGA board. This code was tested in Altera Quartus II. |
| 6 |
2 |
0 |
3 months ago |
leon3-grlib-gpl-mirror/634 |
Git mirror of Gaisler's GRLIB/Leon3 releases |
| 6 |
4 |
1 |
10 months ago |
T-DLA/635 |
None |
| 6 |
2 |
0 |
6 days ago |
pld/636 |
VHDL examples. IFSC lecture notes. |
| 6 |
3 |
0 |
7 years ago |
Plong/637 |
Simple pong implementation in vhdl |
| 6 |
3 |
0 |
9 months ago |
SBA-Library/638 |
SBA IP Cores http://sba.accesus.com |
| 6 |
0 |
0 |
9 years ago |
usb11_phy_translation/639 |
USB 1.1 PHY (VHDL) |
| 6 |
2 |
0 |
8 months ago |
MoxieLite/640 |
Lightweight VHDL implementation of a Moxie Processor |
| 6 |
2 |
0 |
3 years ago |
ADC_LCD_FPGA/641 |
ADC & LCD Interfacing using Verilog & VHDL |
| 6 |
4 |
0 |
3 years ago |
Rhino-Processing-Blocks/642 |
A library of IP cores needed for FPGA-based SDR development using RHINO board with SPARTAN-6 xc6slx150t device. |
| 6 |
0 |
0 |
5 years ago |
Cache-CPU/643 |
MIPS32 instruction subset based processor |
| 6 |
0 |
0 |
6 years ago |
ws2812/644 |
WS2812 RGB LED string driver |
| 6 |
0 |
0 |
1 year, 9 months ago |
computer_aid_design_assignments_CAD/645 |
None |
| 6 |
6 |
0 |
4 years ago |
pre-mipsfpga/646 |
Various Verilog examples to gain knowledge and basic skills before working with MIPSfpga |
| 6 |
1 |
0 |
2 years ago |
MIPS16_CPU/647 |
cpu project for principles of computer organization |
| 6 |
2 |
0 |
9 years ago |
CPLD_USBHxCFloppyEmulator/648 |
CPLD USB HxC Floppy Emulator |
| 6 |
5 |
0 |
2 years ago |
ZYBO_IoT_Vivado/649 |
This is a Vivado project to create an IoT device with ZYBO (Zynq). |
| 6 |
0 |
0 |
Unknown |
Malinki/650 |
Malinki - Hardware Cluster with Switch Fabric for Raspberry Pi |
| 6 |
1 |
0 |
9 years ago |
simplifiedmipscpu/651 |
Complete working simulation of both a single-cycle and pipelined CPU. Implements a subset of the MIPS instruction set. |
| 6 |
0 |
0 |
10 years ago |
backplane/652 |
Soma Backplane Hardware |
| 6 |
1 |
1 |
Unknown |
mz80b_de0/653 |
MZ-80B/MZ-2000 series implementation for Altera DE0 board |
| 6 |
0 |
0 |
3 years ago |
SAYEH-Cache/654 |
implementing SAYEH cache using VHDL |
| 6 |
2 |
1 |
Unknown |
Bonfire/655 |
A implementation of a NoC router with credit based flow control |
| 6 |
3 |
0 |
3 years ago |
mips--/656 |
A dual core MIPS subset CPU written in behavioral, synthesizable VHDL |
| 6 |
3 |
0 |
6 years ago |
CPME48/657 |
Why CP-YOU? Let's CP-ME! 非常简单的8位CPU的VHDL实现，拥有精简的RISC式指令集。更有配套扩展指令集IR48*、汇编器DASM48、高级语言Cheme，你值得拥有。（课程作业，仅供交流，切勿抄袭！） |
| 6 |
2 |
0 |
5 years ago |
hdmi2usb_designs/658 |
Various HDL designs for the Numato Labs/Timvideos HDMI2USB FPGA board |
| 6 |
1 |
0 |
8 years ago |
Sump_Blaze_Core/659 |
VHDL Sump Logic Analyzer |
| 6 |
6 |
0 |
8 months ago |
SDAccel/660 |
SDAccel: Architecture to enable CPU/GPU developers to easily migrate their applications to FPGAs while maintaining and reusing their OpenCL, C, and C++ code in a familiar workflow. |
| 6 |
2 |
0 |
Unknown |
MSHR-rich/661 |
A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency-insensitive hardware accelerators with irregular memory access patterns. |
| 6 |
1 |
1 |
Unknown |
vhdl-cfg/662 |
Playground to explore and compare how configuration is handled by different tools for development of VHDL projects |
| 6 |
1 |
0 |
Unknown |
FreeRTOS-Zybo/663 |
FreeRTOS implemented on the Digilent ZYBO Zynq 7000 |
| 6 |
0 |
2 |
2 years ago |
mz80c_de0/664 |
MZ-80 series implementation for Altera DE0 board |
| 6 |
1 |
0 |
Unknown |
casper_myhdl/665 |
Development of DSP blocks found in CASPER library using MyHDL package and Python |
| 6 |
2 |
1 |
7 years ago |
gbcpu/666 |
A CPU and peripherals implementing the Gameboy (TM) instruction set and functionality |
| 6 |
1 |
0 |
2 months ago |
vhdl-maze-solver/667 |
Cellular Automata Maze Solver Hardware Implementation |
| 6 |
3 |
0 |
5 years ago |
minispartan6/668 |
Projects for the Scarab Minispartan6+ FPGA board |
| 6 |
7 |
0 |
5 years ago |
TE0720-GigaZee-Reference-Designs/669 |
Reference Projects for TE0720 ZYNQ module |
| 6 |
8 |
1 |
5 months ago |
Arcade-Defender_MiSTer/670 |
Arcade: Defender for MiSTer |
| 6 |
0 |
0 |
2 years ago |
maplebus/671 |
Sega Dreamcast Maplebus Transceiver |
| 6 |
9 |
0 |
Unknown |
WM8731-Audio-codec-on-DE10Standard-FPGA-board/672 |
None |
| 6 |
28 |
0 |
Unknown |
Digital-electronics-1/673 |
VHDL course at Brno University of Technology |
| 6 |
10 |
0 |
5 years ago |
VHDL_IP-Cores/674 |
None |
| 6 |
0 |
0 |
3 months ago |
VHDL-LAB/675 |
Some basic electronic structures implemented in VHDL |
| 6 |
1 |
0 |
Unknown |
MDE2/676 |
MASSBUS Disk Emulator Hardware |
| 6 |
3 |
0 |
9 years ago |
VHDL-Snake-Game/677 |
A simple snake game in vhdl - designed for the Spartan-3 Starter Board (work in progress) |
| 6 |
1 |
2 |
7 years ago |
S76D/678 |
Singing Very High Speed Integrated Circuit Hardware Description Language Board |
| 6 |
4 |
0 |
7 years ago |
busblaster_v4/679 |
CPLD designs for the BusBlaster v4 from Dangerous Prototypes |
| 6 |
4 |
0 |
Unknown |
Hardware-Course/680 |
All the verilog code I wrote in hardware Course |
| 6 |
4 |
0 |
2 years ago |
AX7015/681 |
AX7015 |
| 6 |
5 |
0 |
Unknown |
Zedboard-DMA/682 |
None |
| 6 |
6 |
3 |
4 months ago |
aws-fpga-firesim/683 |
AWS Shell for FireSim |
| 6 |
0 |
0 |
4 months ago |
hw-sike/684 |
FPGA implementation of the Supersingular Isogeny Key Encapsulation |
| 6 |
2 |
1 |
4 months ago |
CoreAmstrad/685 |
CoreAmstrad source code, a physical clone of Amstrad from JavaCPC Markus's emulator, currently running on a final FPGA end-user platform : MiST-board. |
| 6 |
3 |
0 |
1 year, 6 months ago |
UniversalPPU/686 |
An FPGA replacement for the graphics chip used in the NES and related systems |
| 6 |
0 |
0 |
Unknown |
Restoring-Divider/687 |
Implementation of restoring division algorithm with VHDL. |
| 6 |
1 |
0 |
3 years ago |
Template-Matching-FPGA/688 |
None |
| 6 |
1 |
0 |
Unknown |
VHDL-School/689 |
My VHDL sources |
| 6 |
1 |
0 |
Unknown |
Zybo-Linux/690 |
A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary to run your own embedded Linux on your ZYBO here. |
| 6 |
9 |
1 |
5 months ago |
Arcade-Xevious_MiSTer/691 |
Arcade: Xevious for MiSTer |
| 6 |
14 |
0 |
1 year, 2 months ago |
GlobalCorrelator/692 |
Firmware for Level-1 Particle Reconstruction |
| 6 |
10 |
3 |
a month ago |
Vectrex_MiSTer/693 |
Vectrex for MiSTer |
| 6 |
1 |
0 |
3 years ago |
1802-pico-basic/694 |
VHDL 1802 Core with TinyBASIC for the Lattice MachXO2 Pico board |
| 6 |
3 |
0 |
8 months ago |
vhdl-digital-design/695 |
VHDL code examples for a digital design course |
| 6 |
7 |
1 |
4 months ago |
ColecoVision_MiSTer/696 |
ColecoVision for MiSTer |
| 6 |
11 |
1 |
5 months ago |
KC705-AD9371/697 |
The implementation of AD9371 on KC705 |
| 6 |
1 |
0 |
3 years ago |
ws2812b-vhdl/698 |
A controller for the WorldSemi WS2812B RGB LEDs written in plain VHDL. |
| 6 |
1 |
0 |
1 year, 9 months ago |
acoustic-levitation/699 |
Acoustic levitation on SoC FPGA (DE0-Nano-SoC). Notice: this repository has moved to GitLab. All issues and pull requests should be created there. |
| 6 |
0 |
0 |
8 months ago |
ulx3s-ghdl-examples/700 |
ulx3s ghdl examples |
| 6 |
3 |
0 |
1 year, 1 month ago |
Nexys-A7-100T-OOB/701 |
None |
| 6 |
1 |
0 |
2 months ago |
VHDL_Handbook_CNE/702 |
CNES Edition of the VHDL Rules |
| 6 |
5 |
2 |
4 years ago |
purisc/703 |
Pipelined Ultimate Reduced Instruction Set Computer |
| 6 |
2 |
2 |
4 years ago |
VHDL-FIR-filters/704 |
Synthesizable FIR filters in VHDL |
| 6 |
11 |
1 |
8 months ago |
sysdesign/705 |
Code base for computer system design |
| 6 |
1 |
0 |
7 months ago |
Verilog_Module/706 |
常用Verilog模块 |
| 6 |
14 |
2 |
3 years ago |
NexysVideo/707 |
None |
| 6 |
1 |
0 |
1 year, 8 months ago |
Architecture-of-CPU-projects/708 |
VHDL , ModelSIM, Quartus, FPGA, Image Processing |
| 6 |
3 |
0 |
4 years ago |
VGA_example/709 |
This repository contains a Vivado 2015.3 Project that runs an example application for the VGA_1.0 IP core. Althrough the core had originally been created for the Avnet Zedboard, this example was created for the Digilent Zybo. |
| 6 |
6 |
0 |
5 years ago |
vhdl-project/710 |
Implementation in VHDL of the Sobel edge detection operator |
| 6 |
2 |
0 |
4 years ago |
zybo-examples/711 |
A series of examples on zybo board for my blog tutorials. |
| 6 |
2 |
0 |
5 years ago |
dmkonst/712 |
An optimized pipelined MIPS CPU written in VHDL |
| 6 |
1 |
1 |
1 year, 3 months ago |
Tiffany/713 |
A scalable MachineForth for PCs, MCUs and FPGAs. |
| 6 |
8 |
0 |
6 years ago |
fpga/714 |
This repository holds all the projects and docs relating to our work with the Xilinx Zynq 7000 series FPGAs. |
| 6 |
2 |
0 |
2 years ago |
GNSS-VHDL/715 |
GNSS codes and signal generation for VHDL. GPS (L1 C/A, L5), Galileo (E1OS, E5). Includes Xilinx ISE testbench and wave configuration files. |
| 6 |
0 |
0 |
8 months ago |
Basic-Computer-design/716 |
A Computer description using VHDL and ModelSim software |
| 6 |
2 |
0 |
2 months ago |
fsva/717 |
FuseSoc Verification Automation |
| 6 |
6 |
0 |
5 years ago |
Papilio-Schematic-Library/718 |
A library of Soft Processors and peripherals that can be used with Webpack schematic editor to build a custom SOC for the Papilio |
| 6 |
3 |
0 |
1 year, 11 months ago |
AX7035/719 |
None |
| 6 |
5 |
0 |
5 years ago |
SDRAM-and-FIFO-for-DE1-SoC/720 |
tutorial |
| 6 |
0 |
1 |
a year ago |
vhlib/721 |
Package of miscellaneous VHDL libraries |
| 6 |
3 |
0 |
6 months ago |
maestro/722 |
A 5 stage-pipeline RV32I implementation in VHDL |
| 6 |
4 |
0 |
8 months ago |
UVVM_Community_VIPs/723 |
Repository for the UVVM community to share VIPs. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/ |
| 6 |
8 |
0 |
4 years ago |
General-Zynq/724 |
A general-design version of zynq |
| 6 |
1 |
0 |
2 years ago |
vhdl_tarning/725 |
VHDL Source Code |
| 6 |
2 |
0 |
2 years ago |
POV/726 |
13113112bit 16FPS POV Display |
| 6 |
1 |
0 |
2 years ago |
pqhw/727 |
None |
| 6 |
1 |
0 |
3 months ago |
Arcade-SuperCobra_MiSTer/728 |
Super Cobra arcade clone for MiSTer. |
| 6 |
4 |
0 |
6 years ago |
lzw_verilog/729 |
LZW Compressoion algorithm in verilog |
| 6 |
2 |
2 |
9 months ago |
DivGMX/730 |
Development Kit |
| 6 |
1 |
0 |
2 years ago |
XNOR-net-Binary-connect/731 |
A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacement of vector-matrix multiplication to “XNOR + Popcount” operation |
| 6 |
1 |
1 |
6 months ago |
b01lers-library/732 |
None |
| 6 |
0 |
4 |
1 year, 26 days ago |
fpga_lib/733 |
Library of utilities such as cores, procedures and functions, commonly shared between FPGA projects. |
| 6 |
9 |
1 |
5 months ago |
Arcade-BombJack_MiSTer/734 |
Arcade: Bomb Jack for MiSTer |
| 6 |
1 |
0 |
10 years ago |
AX8/735 |
The AVR softcore from opencores.org with a makefile and some useable demo code |
| 6 |
7 |
8 |
3 months ago |
Arcade-IremM62_MiSTer/736 |
Irem62 from pace, and mist including Lode Runner, etc |
| 6 |
1 |
0 |
1 year, 6 months ago |
kalman_mppt/737 |
mppt algorithm using kalman filter in VHDL |
| 6 |
2 |
1 |
4 years ago |
gpib/738 |
IEEE-488 (GP-IB, HP-IB) synthesizable core in VHDL |
| 6 |
1 |
0 |
5 years ago |
vhdl-examples/739 |
Unisinos class of Electronics Engineering |
| 6 |
5 |
0 |
4 years ago |
xilinx-zynq-zc702-linuxapplication/740 |
Linux application and Device driver porting on Xilinx Zynq ZC702 board |
| 6 |
2 |
0 |
7 years ago |
bf_cpu/741 |
Brainfuck microprocessor |
| 5 |
0 |
0 |
1 year, 1 month ago |
Grain-128AEAD-VHDL/742 |
The VHDL reference implementation along with optimized versions of the stream cipher Grain-128AEAD |
| 5 |
31 |
3 |
4 years ago |
vhdl-exercise/743 |
A little exercise for VHDL newbies |
| 5 |
23 |
0 |
8 months ago |
cpudesign/744 |
CPU设计的代码站 |
| 5 |
3 |
0 |
5 months ago |
vhdl/745 |
vhdl related contents |
| 5 |
0 |
0 |
3 years ago |
Rotary-encoder-VHDL-design/746 |
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface. |
| 5 |
0 |
0 |
1 year, 8 days ago |
DIYPOV/747 |
One POV Display to rule them all! |
| 5 |
0 |
0 |
a day ago |
GettingStarted_Examples/748 |
This repository contains a collection of reference designs and software application to get starter with Accelize Distribution Platform |
| 5 |
5 |
0 |
4 years ago |
VHDL-Emporium/749 |
Collection of Various created VHDL code |
| 5 |
3 |
0 |
1 year, 11 months ago |
PYNQ-Z2project/750 |
PYNQ-Z2工程 |
| 5 |
0 |
0 |
2 years ago |
Arty_s7_example/751 |
Arty S7 Example with Pmods and MTDS |
| 5 |
8 |
3 |
3 months ago |
TRS-80_MiSTer/752 |
Tandy TRS-80 Model I (port of HT1080Z to MiSTer) |
| 5 |
2 |
0 |
10 months ago |
rmii-firewall-fpga/753 |
RMII Firewall FPGA |
| 5 |
7 |
0 |
1 year, 8 months ago |
Zybo-Z7-20-DMA/754 |
None |
| 5 |
2 |
0 |
5 years ago |
fpu/755 |
FPU written in VHDL |
| 5 |
1 |
0 |
5 years ago |
UART/756 |
UEART Project for DE1 Board |
| 5 |
0 |
0 |
2 years ago |
InfraRed-LED-Controller/757 |
InfraRed decoder written in VHDL + Pulse width modulation on Green LEDs |
| 5 |
1 |
1 |
1 year, 2 months ago |
light8080/758 |
Synthesizable i8080-compatible CPU core. |
| 5 |
0 |
0 |
1 year, 1 month ago |
unicamp/759 |
My unicamp experience |
| 5 |
1 |
0 |
2 years ago |
CADSD-homeworks/760 |
Solutions of Computer Aided Digital System Design (FPGA) Course Homeworks |
| 5 |
0 |
0 |
3 years ago |
RSA_Security_Token/761 |
A Security token system for (two-factor) authentication to Linux / Unix using an FPGA and a PAM-module. Either A: 72-bit or B: 512-bit RSA. Version A is air-gapped. Version B uses USB UART. BSD-3 licensed. |
| 5 |
2 |
0 |
2 years ago |
mips-computer/762 |
A simple computer based on the design in "Digital Design and Computer Architecture - 2nd Edition" |
| 5 |
5 |
0 |
6 years ago |
MIPS-CPU-System/763 |
my mips cpu design in vhdl. support vga and PS/2 keyboard |
| 5 |
1 |
0 |
4 years ago |
vhdl_TCPIP/764 |
TCP IP Stack (including DHCP) implemented in VHDL |
| 5 |
2 |
0 |
5 years ago |
LED-Matrix-with-DE0-Nano-SoC-Board/765 |
tutorial |
| 5 |
3 |
0 |
4 years ago |
firmware-ethernet/766 |
Firmware modules and packages for implementing Ethernet control and data acquisition interfaces on Xilinx FPGAs. |
| 5 |
0 |
0 |
3 years ago |
SAYEH/767 |
SAYEH (Simple Architecture, Yet Enough Hardware) Basic Computer |
| 5 |
0 |
0 |
9 years ago |
fpgaSynths/768 |
Making oldskool music with FPGA VHDL soundchips core and the ZPUino SoC |
| 5 |
0 |
0 |
15 years ago |
t80/769 |
The T80 (VHDL) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,t80) |
| 5 |
3 |
0 |
3 years ago |
Arty-GPIO/770 |
None |
| 5 |
3 |
0 |
2 years ago |
AX7103/771 |
None |
| 5 |
1 |
0 |
3 years ago |
afu-walkthrough/772 |
Simple overview of the PSL-AFU Interface for CAPI |
| 5 |
1 |
0 |
3 months ago |
erbium/773 |
Business Rule Engine Hardware Accelerator |
| 5 |
2 |
0 |
2 months ago |
blp/774 |
Blinking Led Project |
| 5 |
5 |
0 |
4 months ago |
QL_MiSTer/775 |
Sinclair QL for MiSTer |
| 5 |
1 |
1 |
13 days ago |
IPDBG/776 |
IPDBG |
| 5 |
8 |
0 |
6 years ago |
zynq_echo_servers/777 |
UDP and TCP echo servers using lwIP RAW API running on Xilinx Zynq Platform |
| 5 |
1 |
0 |
5 years ago |
speccy-wxeda/778 |
Порт конфигурации Reverse u16_speccy на плату ZrTech WXEDA |
| 5 |
2 |
0 |
5 years ago |
CCD_Cam/779 |
Cam interface to FPGA using ADV7180 |
| 5 |
3 |
0 |
6 years ago |
fpga-sdr-platform/780 |
FPGA SDR platform: AD9963 + XC6SLX9 + CY7C68013 |
| 5 |
1 |
0 |
5 months ago |
THCOMIPS16e/781 |
Yet Another Implementation of THCO MIPS16e |
| 5 |
3 |
0 |
9 years ago |
async_8b10b_encoder_decoder/782 |
Async 8b/10b enc/dec |
| 5 |
1 |
0 |
3 years ago |
present-vhdl/783 |
Implementation of the PRESENT lightweight block cipher in VHDL. |
| 5 |
7 |
2 |
14 days ago |
PandABlocks-FPGA/784 |
VHDL functional blocks with their simulations and test sequences |
| 5 |
1 |
0 |
4 days ago |
MasterThesis/785 |
VHDL implementation of a customizable CNN |
| 5 |
1 |
1 |
6 years ago |
Guimauve2ooo/786 |
VGA output for Apple //c computers |
| 5 |
2 |
1 |
1 year, 2 months ago |
FPGA-Miner/787 |
💰 A simplified version of an FPGA bitcoin miner 💰 |
| 5 |
10 |
0 |
3 years ago |
cours-tlm/788 |
Supports pour le cours de « Modélisation Transactionnelle des Systèmes sur Puces » |
| 5 |
0 |
0 |
10 months ago |
Computer-aided-Design/789 |
The implementation of some modules and basic projects of CAD in VHDL |
| 5 |
0 |
0 |
4 months ago |
VHDL-FPGA-LAB_PROJECTS/790 |
Lab Assigments, Projects for digital systems II Lecture (EEM334) |
| 5 |
0 |
0 |
2 years ago |
arm_nyuzi/791 |
a multi-cpu with gpgpu project running on the xilinx zynq board(zc706) |
| 5 |
2 |
0 |
7 years ago |
LevOS/792 |
A hobbyist operating system. |
| 5 |
1 |
2 |
2 months ago |
yaaes/793 |
Yet Another AES implementation in hardware. |
| 5 |
1 |
0 |
2 years ago |
donkey-kong-fpga/794 |
FPGA implementation of arcade game Donkey Kong |
| 5 |
4 |
0 |
6 months ago |
Learning-data-backup/795 |
本科学习资料备份 |
| 5 |
2 |
0 |
9 months ago |
Handwritten-Digit-Recognition-Painter/796 |
A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog. |
| 5 |
2 |
0 |
7 hours ago |
theremin/797 |
Open source digital FPGA based theremin project |
| 5 |
1 |
0 |
6 years ago |
cpu/798 |
a simple cpu written by vhdl. |
| 5 |
1 |
0 |
4 years ago |
sparcv8-monocycle/799 |
Procesador monociclo arquitectura SPARC V8 modelado en VHDL. |
| 5 |
3 |
2 |
3 years ago |
ZedBoardAudio/800 |
AXI Slave Audio Component. |
| 5 |
1 |
1 |
1 year, 11 months ago |
FPGA_1942/801 |
FPGA 1942 arcade game |
| 5 |
2 |
0 |
11 years ago |
acqboard/802 |
Soma 8+2 Acquisition Module, hardware and software |
| 5 |
0 |
0 |
3 years ago |
MyRISC/803 |
VHDL implementation of a 16-bit RISC processor targeting the BASYS3 FPGA |
| 5 |
3 |
0 |
4 years ago |
aes-dom/804 |
DOM Protected Hardware Implementation of AES |
| 5 |
2 |
0 |
8 months ago |
Gr0estl-Miner/805 |
Gr0estl mining algo FPGA implementation by AtomMiner |
| 5 |
9 |
0 |
2 years ago |
ComputerOrganizationDesign/806 |
计算机组成课程资料 |
| 5 |
0 |
0 |
9 years ago |
fpgapong/807 |
Fpga implementation of pong |
| 5 |
8 |
0 |
3 years ago |
Zybo-Open-Source-Video-IP-Toolbox/808 |
A few tools for doing video processing on the Zybo FPGA board using VHDL |
| 5 |
0 |
0 |
5 years ago |
2048-DE1/809 |
VHDL implementation of 2048 Game on Altera DE1 FPGA Board |
| 5 |
4 |
0 |
8 years ago |
umn_simaudio/810 |
Univ. of MN Simultaneous Audio Recording Interface Software and Firmware |
| 5 |
5 |
2 |
5 years ago |
logi-mt9v034/811 |
None |
| 5 |
0 |
0 |
1 year, 1 month ago |
SoC-Nios/812 |
Building an example System on Chip (SoC) using Nios II processor. |
| 5 |
4 |
0 |
8 months ago |
AtomGodilVideo/813 |
New Video Adapter for Acorn Atom implemented in a GODIL FPGA |
| 4 |
1 |
0 |
2 years ago |
CPU31/814 |
31条mips指令的单周期cpu(非流水线） |
| 5 |
0 |
0 |
2 years ago |
dungeon-escape-vhdl-game/815 |
Dungeon Escape VHDL Game |
| 5 |
1 |
0 |
6 days ago |
DesertFoxCPU/816 |
None |
| 5 |
2 |
1 |
1 year, 2 months ago |
fast-p2a/817 |
None |
| 5 |
2 |
0 |
8 years ago |
YaGraphCon/818 |
Yet Another Graphics Controller |
| 5 |
2 |
0 |
8 years ago |
MIDI-Synthesizer/819 |
None |
| 5 |
6 |
0 |
1 year, 3 months ago |
iota_vhdl_pow/820 |
None |
| 5 |
1 |
0 |
7 months ago |
bonfire-soc-fireant/821 |
Bonfire SoC running on FireAnt FPGA Board |
| 5 |
1 |
0 |
11 months ago |
CPU-VHDL/822 |
Um simples CPU desenvolvido em VHDL |
| 5 |
2 |
0 |
5 months ago |
apple2fpga/823 |
port of Stephen A. Edwards apple2fpga to ULX3S |
| 5 |
1 |
0 |
4 years ago |
color_maker-s3esk/824 |
A simple VGA output tester for the Xilinx Spartan-3E starter kit board. |
| 5 |
0 |
0 |
5 years ago |
libcapi/825 |
A library of things IBM CAPI related including common C and RTL code for AFUs. |
| 5 |
3 |
0 |
6 years ago |
Vampire600/826 |
Core for the Vampire 600 Amiga accelerator project |
| 5 |
3 |
0 |
2 years ago |
Game-of-Balance-on-Nexys4DDR/827 |
Game of Balance is an accelerometer based maze navigation game, with added features of score and life, that is built on Nexys 4 DDR development board. |
| 5 |
5 |
0 |
2 years ago |
CNN_DPR/828 |
Landmark Detection with CNN on FPGA including DPR |
| 5 |
2 |
0 |
7 months ago |
hashpipe/829 |
SHA-256 Bitcoin hashing engine implemented as a systolic pipeline |
| 5 |
5 |
0 |
5 years ago |
udp_ip_stack/830 |
This repository contains a copy of the "1G eth UDP / IP Stack" opencores.org project(http://opencores.org/project,udp_ip_stack) and add a fully working mac layer for the Virtex 6 ML605 board. Moreover it provides a Qt benchmark software. |
| 5 |
24 |
0 |
9 months ago |
2019_FPGA_Design/831 |
This repository is for 2019 NCKUEE FPGA System Design course |
| 5 |
1 |
0 |
1 year, 22 days ago |
single-cycle-processor/832 |
An implementation of the simplest single cycle processor. |
| 5 |
3 |
0 |
9 years ago |
mkjpeg/833 |
EV_JPEG_ENC core is intended to encode raw bitmap images into JPEG compliant coded bit stream. JPEG baseline encoding method is used. • LICENSE: GNU LGPL v3.0 |
| 5 |
0 |
0 |
2 years ago |
snake-verilog/834 |
This program is written in verilog . |
| 5 |
4 |
0 |
2 years ago |
mrf-openevr/835 |
Open source Event Receiver implementation |
| 5 |
2 |
0 |
2 years ago |
Unum_matrix_multiplier/836 |
Matrix-multiply unit for Posit number with quire registers |
| 5 |
0 |
0 |
4 years ago |
SynADT/837 |
Data Structures (Linked List, Binary Tree, HashTable, Vectors) in HLS using SysAlloc. |
| 5 |
0 |
0 |
3 years ago |
bcomp2/838 |
8-bit computer |
| 5 |
1 |
0 |
5 years ago |
ghdl/839 |
A mirror of GHDL - a VHDL language front-end for GCC and LLVM |
| 5 |
3 |
0 |
a month ago |
CryptoHDL/840 |
A list of VHDL codes implementing cryptographic algorithms |
| 5 |
0 |
0 |
7 months ago |
Demo_project/841 |
None |
| 5 |
0 |
0 |
8 years ago |
BLOB-Detection/842 |
Blob Detection in HDL |
| 5 |
0 |
0 |
11 years ago |
noc-ni/843 |
Network Interface for a NoC implemented in VHDL |
| 5 |
11 |
1 |
9 years ago |
welecw2000a/844 |
Redesigned firmware for Welec W2000A series digital storage oscilloscopes |
| 5 |
12 |
0 |
4 years ago |
xapp1026/845 |
LightWeight IP Application Examples for Xilinx FPGA |
| 5 |
3 |
1 |
2 years ago |
OpenNX4/846 |
New FPGA firmware for Barco NX4 LED video tiles, supporting many features handy for hackers, and use of an inexpensive linux SBC as a tile controller |
| 5 |
1 |
1 |
4 years ago |
TMC5130FPGA/847 |
None |
| 5 |
2 |
3 |
3 years ago |
Zybo-DMA/848 |
None |
| 5 |
0 |
0 |
6 years ago |
vhdl-simple-processor/849 |
Implementation of a simple processor using VHDL for logic synthesis in FPGA |
| 5 |
1 |
0 |
4 years ago |
ftdi-async-fifo/850 |
FTDI FT2232H Asynchronous FIFO communication with FPGA over USB |
| 5 |
0 |
0 |
6 years ago |
sha256_core/851 |
None |
| 5 |
0 |
0 |
a year ago |
LSTM_FPGA/852 |
~ Implementation of LSTM ANN in FPGA with VHDL |
| 5 |
2 |
0 |
1 year, 5 months ago |
sdr4/853 |
AD9363 + XC6SLX9 board |
| 5 |
5 |
1 |
5 months ago |
Arcade-MCR3Mono_MiSTer/854 |
Arcade: MCR3 Monoboard games |
| 5 |
6 |
1 |
5 years ago |
SOC_tutorial/855 |
DE1-SOC |
| 5 |
5 |
0 |
6 years ago |
SpaceWireRMAPTargetIP/856 |
None |
| 5 |
1 |
0 |
6 years ago |
MadeAComputerIn20Days/857 |
Made a computer in 20 days. (well actually, more) |
| 5 |
0 |
0 |
9 years ago |
microcpu/858 |
Soft core simple cpu |
| 5 |
1 |
0 |
10 years ago |
fx2fpga/859 |
HW:PCB & VHDL to interface an FX2LP chip to a Digilent S3BOARD. |
| 5 |
2 |
1 |
1 year, 11 months ago |
CNN-for-modulation-recognition-based-on-FPGA/860 |
None |
| 5 |
0 |
0 |
9 months ago |
MeowRouter-top/861 |
Top for MeowRouter |
| 5 |
0 |
0 |
4 years ago |
SysAlloc/862 |
SysAlloc, a FPGA implemented hardware memory allocator for heterogeneous systems. |
| 5 |
5 |
0 |
3 years ago |
md5/863 |
MD5 in VHDL |
| 5 |
1 |
0 |
4 years ago |
vhdl_verification/864 |
Examples and design pattern for VHDL verification |
| 5 |
0 |
0 |
9 months ago |
High_Level_Synthesis/865 |
None |
| 5 |
4 |
0 |
5 years ago |
AVR-Processor/866 |
VHDL implementation of an AVR processor. |
| 5 |
4 |
0 |
4 years ago |
logic_analyzer/867 |
FPGA-Based Logic Analyzer |
| 5 |
0 |
0 |
9 years ago |
Computer/868 |
None |
| 5 |
1 |
0 |
2 years ago |
PWM-in-VHDL/869 |
PWM in VHDL |
| 5 |
0 |
0 |
4 years ago |
ghdl-example/870 |
ghdl example |
| 5 |
2 |
0 |
1 year, 6 months ago |
My_Design/871 |
带有tlb的五级流水CPU |
| 5 |
4 |
0 |
6 years ago |
THCO-MIPS-CPU/872 |
Computer Organization course project:THCO-MIPS CPU |
| 5 |
3 |
0 |
3 years ago |
parti-fpga/873 |
FPGA-based data partitioning |
| 5 |
0 |
0 |
4 years ago |
pyLeros/874 |
Tiny accumulator based microprocessor |
| 5 |
0 |
1 |
1 year, 1 month ago |
nscscc_test/875 |
nscscc test script |
| 5 |
0 |
0 |
2 years ago |
CAD_2018/876 |
Some of small codes and implementation of modules in Computer Aided Design in VHDL by ActiveHDL |
| 5 |
2 |
10 |
29 days ago |
mrisc32-a1/877 |
A pipelined, in-order, scalar implementation of the MRISC32 ISA |
| 5 |
0 |
0 |
2 years ago |
mastermind/878 |
FPGA implementation of the popular logic game using VHDL and Altera DE1 |
| 5 |
3 |
1 |
2 years ago |
ultrasonic-levitation-with-Xilinx-Zynq/879 |
This github contains the Vivado project, PCB schematic and control software for levitation framework at Bristol University |
| 5 |
4 |
0 |
9 months ago |
SHA-256/880 |
An SHA-256 module implementation in VHDL. Based on NIST FIPS 180-4. |
| 5 |
10 |
2 |
3 years ago |
Zybo-hdmi-out/881 |
None |
| 5 |
4 |
0 |
2 years ago |
Kalman-Filter-verilog/882 |
Hey guys this the project where i have implemented the Kalman filter for MPPT for solar PV module |
| 5 |
1 |
0 |
27 days ago |
rv16poc/883 |
16 bit RISC-V proof of concept |
| 5 |
0 |
0 |
3 years ago |
vhdl-snake/884 |
Snake game with PS2 and VGA drivers written in VHDL for the Nexys 2 development board |
| 5 |
1 |
0 |
a month ago |
RISCV-32I/885 |
RISC V 32 bit Base ISA Implementation. |
| 5 |
0 |
0 |
7 years ago |
kanto/886 |
Kanto Audio Player |
| 5 |
2 |
0 |
2 years ago |
euryspace/887 |
Space Communication System based on CCSDS recommandations |
| 5 |
3 |
0 |
3 years ago |
ascon_hardware/888 |
Hardware implementations of the authenticated encryption design ASCON |
| 5 |
0 |
1 |
1 year, 4 months ago |
Moose/889 |
Implementation of RISC V architecture in VHDL |
| 5 |
6 |
0 |
7 years ago |
BitRush/890 |
An open source project for bitcoin mining on an FPGA |
| 5 |
2 |
0 |
2 years ago |
adpll/891 |
All digital PLL |
| 5 |
3 |
0 |
4 years ago |
hdmi-audio/892 |
HDMI Audio/Video signal generation for HW emulators of retro comuters |
| 5 |
0 |
0 |
8 years ago |
sdl_vhdl/893 |
just use SDL to display a simulated memory region which will be a framebuffer in a VHDL project. |
| 5 |
3 |
21 |
4 months ago |
FPGA_MNIST/894 |
None |
| 5 |
0 |
0 |
2 months ago |
icestick-remote/895 |
Remote control in VHDL, which fits on a Lattice icestick. |
| 5 |
1 |
0 |
2 years ago |
snickerdoodle-hls-data-mover/896 |
A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S defaults to 8 bits and AXI-MM to 64 bits) |
| 5 |
4 |
1 |
7 months ago |
psi_fix/897 |
Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation) |
| 5 |
2 |
0 |
1 year, 4 months ago |
DCNN-Accelerator/898 |
Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images. |
| 6 |
0 |
0 |
6 years ago |
PapilioPro-AnimatedShapes/899 |
Driving the VGA protocol, displaying some animated shapes on an FPGA |
| 5 |
2 |
0 |
4 years ago |
DMXControl/900 |
A vhdl implementation of a DMX 512 Controller on a Xilink FPGA |
| 5 |
4 |
0 |
2 years ago |
AX7020/901 |
None |
| 5 |
3 |
0 |
4 years ago |
norx-hw/902 |
Reference implementation (hardware) |
| 5 |
2 |
0 |
6 years ago |
ofdm/903 |
None |
| 5 |
10 |
0 |
1 year, 2 months ago |
realtimeEMTP/904 |
FPGA and CPU-Based power system's simulator |
| 5 |
0 |
0 |
2 years ago |
ip_cores/905 |
Verilog IP Cores & Tests |
| 5 |
3 |
0 |
3 months ago |
de10-nano-examples/906 |
DE10 Nano Sample Cores |
| 5 |
3 |
3 |
4 months ago |
Oric_Mist_48K/907 |
Oric Atmos Mist core |
| 5 |
1 |
3 |
1 year, 3 months ago |
Music5000/908 |
FPGA implementation of the 1980's "Music 5000" wavetable synthesiser |
| 4 |
0 |
0 |
4 years ago |
FPGAuartCamera/909 |
Trying connect 8bit Camera to FPGA with translate data on UART |
| 4 |
4 |
0 |
3 years ago |
socz80_espier_iii_v105/910 |
Port of William R. Sowerbutts' to a cheap Spartan6 board (ESPIER_III V105) |
| 4 |
0 |
0 |
2 years ago |
super-duper-nes/911 |
Super-duper NES project! |
| 4 |
1 |
6 |
2 years ago |
OS2018spring-projects-g05/912 |
Dual-core MIPS CPU SoC |
| 4 |
1 |
8 |
1 year, 4 months ago |
risc/913 |
💻🍁 A design for a RISC |
| 4 |
2 |
1 |
1 year, 1 month ago |
mining-shell/914 |
Development shell repo for creation of fpga bitstreams |
| 4 |
0 |
0 |
9 years ago |
mp3/915 |
pipelined cpu for ece411 |
| 4 |
8 |
0 |
4 years ago |
Zynq_Custom_Core_Templates/916 |
Sample HDL Code that Interfaces to the Zynq AXI Bus |
| 4 |
0 |
1 |
1 year, 9 months ago |
Odyssey2_MiSTer/917 |
Odyssey2/Videopac for MiSTer |
| 4 |
0 |
0 |
1 year, 4 months ago |
ghdl-tutorial/918 |
simple ghdl and ikarus tutorial |
| 4 |
0 |
1 |
1 year, 5 months ago |
t80/919 |
Configurable cpu core that supports Z80, 8080 and gameboy instruction sets. |
| 4 |
1 |
0 |
3 years ago |
CE208-CA-Lab/920 |
Computer Architecture Laboratory Material and Reports |
| 4 |
0 |
1 |
3 years ago |
VDHL-SD-Library/921 |
A VHDL-Library for reading a SD-Card with a FPGA in a small test project |
| 4 |
7 |
0 |
10 months ago |
fpga_cyclone4/922 |
正点原子开拓者&新起点FPGA开发板例程 |
| 4 |
0 |
0 |
6 months ago |
fins/923 |
Firmware IP Node Specification (FINS) Code Generator |
| 4 |
0 |
0 |
4 years ago |
-The_King_of_Fighters/924 |
digital logic design course's big project |
| 4 |
1 |
0 |
1 year, 1 month ago |
efficient_checksum-offload-engine/925 |
Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream interface. |
| 4 |
8 |
1 |
20 days ago |
Arcade-Astrocade_MiSTer/926 |
Arcade games on Bally Astrocade Hardware |
| 4 |
2 |
0 |
9 days ago |
VHDPlus_Libraries_and_Examples/927 |
This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with future updates. |
| 4 |
2 |
0 |
4 years ago |
altera-de1-mp3-recorder-vhdl/928 |
"Portable Recorder" is a system made for the Altera DE1 board using Quartus 2 version 9.1 and VHDL and Verilog languages. The system can record and play back audio from the microphone or other external sources (PC, stereo, mp3 player). |
| 4 |
3 |
0 |
7 years ago |
Papilio_System_On_Chip/929 |
Build your custom Arduino compatible microcontroller using a schematic editor. |
| 4 |
0 |
0 |
10 years ago |
calculator/930 |
calculator for fpga with vga display |
| 4 |
1 |
0 |
4 years ago |
mig_ddr3_wrapper_virtex6/931 |
MIG DDR3 Wrapper for FPGA Virtex 6 |
| 4 |
1 |
0 |
3 years ago |
DigitalClockWithVGA_VHDL/932 |
DigitalClockWithVGA_VHDL can ported to any FPGA board to display two adjustable digital clocks with adjustable colors. The code was tested on Xilinx Spartan 3E and Altera DE0 boards. Detailed information: http://mozcelikors.com |
| 4 |
2 |
3 |
1 year, 8 months ago |
Zybo-Z7-10-DMA/933 |
None |
| 4 |
1 |
0 |
3 years ago |
CSI2Rx/934 |
None |
| 4 |
1 |
0 |
10 years ago |
sdram_controller/935 |
Scratch DDR SDRAM Controller |
| 4 |
0 |
0 |
3 months ago |
misc_hdl_module/936 |
release 1 |
| 4 |
0 |
0 |
2 years ago |
computer_architecture_project/937 |
Our project material for the Computer Architecture course for Computer Engineering students at Politecnico di Torino (Polytechnic University of Turin) |
| 4 |
0 |
1 |
8 months ago |
sgen/938 |
SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset is divided into several chunks that are processed during several cycles, thus allowing a reduced use of resources. The size of these chunks is referred as the streaming width. It outputs a Verilog file that can be used for FPGAs. |
| 4 |
5 |
1 |
4 months ago |
Arcade-Asteroids_MiSTer/939 |
Atari Asteroids for MiSTer |
| 4 |
1 |
0 |
11 years ago |
yavga/940 |
Yet Another VGA |
| 4 |
1 |
0 |
3 years ago |
Approximate-Computing/941 |
Adder and multipliers (VHDL) |
| 4 |
2 |
0 |
4 days ago |
PipeWork/942 |
Pipework components is VHDL library for NoC(Network on Chip). |
| 4 |
0 |
0 |
4 years ago |
Apple_II_vhdl/943 |
Apple ][+ implemented in VHDL for FPGAs |
| 4 |
1 |
0 |
8 years ago |
DVI-VHDL-Project/944 |
None |
| 4 |
1 |
0 |
9 years ago |
fpga_pres/945 |
FPGA Presentation for Open Source Bridge 2010 |
| 4 |
3 |
0 |
1 year, 7 months ago |
fpga-colossus/946 |
Implementation of part of the World-War-II code-breaking machine 'Colossus' on an FPGA |
| 4 |
1 |
1 |
4 years ago |
Playground/947 |
Develop the directors structure and testing infrastructure for CoreLib |
| 4 |
1 |
0 |
1 year, 9 months ago |
fpga_rbpi_sdr/948 |
FPGA firmware for SDR on Raspberry Pi 3 |
| 4 |
1 |
0 |
2 years ago |
blake2/949 |
VHDL implementation of BLAKE2 cryptographic hash and message authentication code (MAC) |
| 4 |
6 |
0 |
3 years ago |
beginning-fpga-programming-metal/950 |
Source code for 'Beginning FPGA: Programming Metal' by Aiken Pang and Peter Membrey |
| 4 |
3 |
0 |
2 years ago |
PongGameVHDL/951 |
Here is the code of my digital design term project, which is an implementation of the classic arcade game Pong in VGA using basys3 board. The game is implemented using VHDL hardware description language. You can find a video description from the link: https://www.youtube.com/watch?v=LqOlgilpCYc&t=36s |
| 4 |
0 |
0 |
1 year, 6 months ago |
USTC_CS_digital_labs/952 |
Verilog code of Digital circuit lab in 2018 Fall |
| 4 |
1 |
0 |
3 years ago |
eel5105/953 |
Repo do Projeto Final de Circuitos e Técnicas Digitais 16.1 da UFSC. |
| 4 |
2 |
0 |
7 years ago |
vhdl-examples/954 |
VHDL example code |
| 4 |
5 |
3 |
3 years ago |
APS2-Comms/955 |
HDL modules for ethernet communications with APS2 and TDM modules |
| 4 |
6 |
0 |
5 months ago |
WallTree/956 |
A VHDL code generator for wallace tree multiplier |
| 4 |
1 |
0 |
2 years ago |
FPGA-Acceleration-of-Canny-Edge-Detection-Algorithm/957 |
HW and SW based implementation of Canny Edge Detection Algorithm. |
| 4 |
2 |
0 |
7 months ago |
cocotbExamples/958 |
None |
| 4 |
3 |
0 |
6 years ago |
ml605-pcie-sg-dma/959 |
PCIe Scatter-Gather DMA Engine implemented on the Virtex-6 ML605 Evaluation Board |
| 4 |
1 |
0 |
6 months ago |
HLS/960 |
HLS demos of image processing |
| 4 |
1 |
1 |
1 year, 9 months ago |
caleidoscope/961 |
None |
| 4 |
1 |
0 |
7 years ago |
sigma_delta_dac_dual_loop/962 |
2nd order Sigma-Delta DAC |
| 4 |
1 |
0 |
9 years ago |
VHDL/963 |
Hardware design VHDL code |
| 4 |
1 |
0 |
3 years ago |
WOW_CROW/964 |
A Somatic Game on FPGA |
| 4 |
1 |
0 |
3 years ago |
Microprocessor-Projects/965 |
A set of two microprocessor projects as a part of EE 309 / 337 at IIT Bombay. |
| 4 |
1 |
0 |
3 years ago |
LongLiveFPGA/966 |
Final Project - Long Live FPGA Group - MIPS Microprocessor Implementation |
| 4 |
1 |
0 |
1 year, 8 months ago |
FAST-ANT/967 |
None |
| 4 |
5 |
0 |
6 years ago |
1553-Firmware/968 |
Contains VHDL implementing an 8085, Holt HI-6130 1553 IC, and Memory. Also includes firmware used to demo the system. |
| 4 |
1 |
2 |
8 years ago |
h264/969 |
motion estimation in VHDL |
| 4 |
2 |
1 |
2 years ago |
ip-cores/970 |
⚙️ IP Cores for Xilinx FPGA Devices |
| 4 |
0 |
0 |
8 months ago |
Pong-Game-FPGA/971 |
FPGA Game project with HDMI driver |
| 4 |
4 |
0 |
5 years ago |
fpga_video/972 |
Manipulation of HDMI video with MicroBlaze. Xilinx Spartan 6. |
| 4 |
1 |
3 |
9 months ago |
8bitComputer/973 |
8 bit CPU by VHDL |
| 4 |
1 |
0 |
4 months ago |
Sys0800/974 |
VHDL implementation of vintage TMS0800 calculator chip |
| 4 |
2 |
0 |
2 months ago |
atlas-altiroc-daq/975 |
None |
| 4 |
0 |
0 |
9 days ago |
gbaHD/976 |
A GBA to DVI converter. |
| 4 |
0 |
0 |
6 years ago |
flappy_vhdl/977 |
A Flappy bird implementation in VHDL for a Digital Circuits course at Unicamp. |
| 4 |
1 |
1 |
6 years ago |
SimpleRISC-VHDL/978 |
Implementation of Simple RISC Processor in VHDL |
| 4 |
0 |
0 |
4 years ago |
WPA2-HDL/979 |
[paused] WPA2 related cores written in VHDL |
| 4 |
3 |
0 |
9 years ago |
Tri-mode-Ethernet-MAC/980 |
Creates an Ethernet connection through the embedded Tri-mode Ethernet MAC of the Virtex-5 FPGA. |
| 4 |
1 |
0 |
4 years ago |
ZYBO_Smart_car_demo/981 |
None |
| 4 |
0 |
0 |
2 years ago |
AXI4_Master/982 |
A VHDL implementation of an AXI4 Master |
| 4 |
1 |
0 |
3 years ago |
AtlysSGM/983 |
None |
| 4 |
1 |
0 |
2 years ago |
UltraZed_PCIe/984 |
UltraZed and PCIe example |
| 4 |
3 |
0 |
2 years ago |
Arty-A7-35-Pmod-VGA/985 |
None |
| 4 |
2 |
0 |
2 years ago |
Arty-S7-50-GPIO/986 |
None |
| 4 |
0 |
0 |
5 years ago |
imagesensor_system/987 |
This document is a project of cmos image sensor system. The doc mainly includes LUPA4000 Cmos sensor driving, SDRAM storage, LVDS data readout etc. The code is written in VHDL. |
| 4 |
1 |
0 |
2 years ago |
AX7021/988 |
None |
| 4 |
7 |
0 |
5 years ago |
Zynq-Configuration-Controller/989 |
A configuration controller solution allowing a Zynq device to configure downstream FPGAs |
| 4 |
5 |
0 |
1 year, 3 months ago |
Silicon_Peasant/990 |
None |
| 4 |
1 |
10 |
1 year, 1 month ago |
Phoenix2600/991 |
Atari 2600 Core for CollectorVision Phoenix |
| 4 |
2 |
0 |
3 years ago |
fpga-mmu/992 |
internship |
| 4 |
2 |
0 |
11 months ago |
Zynq-TX-UTT/993 |
Project about hardware acceleration performance on a Xilinx Zynq-7000 SoC ZC702 |
| 4 |
2 |
0 |
1 year, 9 months ago |
Verilog_Jump/994 |
An FPGA version of the WeChat Jump(跳一跳) game using Nexys4 DDR and its onboard accelerometer. |
| 4 |
4 |
0 |
1 year, 1 month ago |
Zedboard_Intergrating_HLS_IP_AND_DDR/995 |
This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART. |
| 4 |
4 |
0 |
8 months ago |
LPC2LCD/996 |
LCD adapter for the LPC bus of the OG xbox |
| 4 |
9 |
3 |
5 months ago |
Arcade-Scramble_MiSTer/997 |
Arcade: Scramble for MiSTer |
| 4 |
1 |
1 |
3 years ago |
FPGA_Guitar_pedal/998 |
Guitar pedal I made for my FPGA (altera) class at school. |
| 4 |
4 |
0 |
4 years ago |
Polar-Codes-Hardware-VHDL/999 |
Polar Codes Implementation on Vhdl |
| 4 |
1 |
0 |
2 years ago |
FPGA-Homework/1000 |
Dr.SahebZamani FPGA Homework |
