数字系统设计练习（七）—— 简单数码管显示
一、实验硬软件环境：
- EDA软件：Vivado2019
- 实验开发板：Basys3 FPGA套件
二、实验内容：
实现的电路功能为：本次实验中实现一个简单的数码管显示控制电路，要求四个按键对应4个数码管，当按键1按下， 数码管1显示1；当按键2按下， 数码管2显示2；当按键3按下，数码管3显示3；当按键4按下，数码管显示4；没有按键的时候，数码管同时显示0。
数码管的基本原理及实验板数码管对应的管脚配置分别如图所示。
三、 具体实现
- 设计源码
View Code1 `timescale 1ns / 1ps 2 ////////////////////////////////////////////////////////////////////////////////// 3 // Company: 4 // Engineer: 5 // 6 // Create Date: 2020/08/14 20:01:14 7 // Design Name: 8 // Module Name: nixietube 9 // Project Name: 10 // Target Devices: 11 // Tool Versions: 12 // Description: 13 // 14 // Dependencies: 15 // 16 // Revision: 17 // Revision 0.01 - File Created 18 // Additional Comments: 19 // 20 ////////////////////////////////////////////////////////////////////////////////// 21 22 23 module nixietube( 24 input [3:0] key1, 25 output reg [3:0] key2, 26 output reg [7:0] out 27 ); 28 29 always @(key1) 30 begin 31 case(key1) 32 4'b0001: 33 begin 34 key2 = 4'b1110; out = 8'b1001_1110; 35 end 36 4'b0010: 37 begin 38 key2 = 4'b1101; out = 8'b0010_0100; 39 end 40 4'b0100: 41 begin 42 key2 = 4'b1011; out = 8'b0000_1100; 43 end 44 4'b1000: 45 begin 46 key2 = 4'b0111; out = 8'b1001_1000; 47 end 48 default: 49 begin 50 key2 = 4'b0000; out = 8'b0000_0010; 51 end 52 endcase 53 end 54 endmodule
- 仿真代码
View Code
1 `timescale 1ns / 1ps 2 ////////////////////////////////////////////////////////////////////////////////// 3 // Company: 4 // Engineer: 5 // 6 // Create Date: 2020/08/15 16:04:31 7 // Design Name: 8 // Module Name: nixietube_tb 9 // Project Name: 10 // Target Devices: 11 // Tool Versions: 12 // Description: 13 // 14 // Dependencies: 15 // 16 // Revision: 17 // Revision 0.01 - File Created 18 // Additional Comments: 19 // 20 ////////////////////////////////////////////////////////////////////////////////// 21 22 23 module nixietube_tb; 24 reg [3:0] key; 25 wire [3:0] switch; 26 wire [7:0] out; 27 28 nixietube uut( 29 .key(key), 30 .switch(switch), 31 .out(out) 32 ); 33 34 initial 35 begin 36 key = 4'b0000; 37 #100 key = 4'b0001; 38 #100 key = 4'b0010; 39 #100 key = 4'b0100; 40 #100 key = 4'b1000; 41 #100; 42 end 43 endmodule
- 波形图
- 约束文件
View Code
1 set_property PACKAGE_PIN R2 [get_ports key[0]] 2 set_property IOSTANDARD LVCMOS33 [get_ports key[0]] 3 set_property PACKAGE_PIN T1 [get_ports key[1]] 4 set_property IOSTANDARD LVCMOS33 [get_ports key[1]] 5 set_property PACKAGE_PIN U1 [get_ports key[2]] 6 set_property IOSTANDARD LVCMOS33 [get_ports key[2]] 7 set_property PACKAGE_PIN W2 [get_ports key[3]] 8 set_property IOSTANDARD LVCMOS33 [get_ports key[3]] 9 set_property PACKAGE_PIN W4 [get_ports switch[0]] 10 set_property IOSTANDARD LVCMOS33 [get_ports switch[0]] 11 set_property PACKAGE_PIN V4 [get_ports switch[1]] 12 set_property IOSTANDARD LVCMOS33 [get_ports switch[1]] 13 set_property PACKAGE_PIN U4 [get_ports switch[2]] 14 set_property IOSTANDARD LVCMOS33 [get_ports switch[2]] 15 set_property PACKAGE_PIN U2 [get_ports switch[3]] 16 set_property IOSTANDARD LVCMOS33 [get_ports switch[3]] 17 set_property PACKAGE_PIN W7 [get_ports out[7]] 18 set_property IOSTANDARD LVCMOS33 [get_ports out[7]] 19 set_property PACKAGE_PIN W6 [get_ports out[6]] 20 set_property IOSTANDARD LVCMOS33 [get_ports out[6]] 21 set_property PACKAGE_PIN U8 [get_ports out[5]] 22 set_property IOSTANDARD LVCMOS33 [get_ports out[5]] 23 set_property PACKAGE_PIN V8 [get_ports out[4]] 24 set_property IOSTANDARD LVCMOS33 [get_ports out[4]] 25 set_property PACKAGE_PIN U5 [get_ports out[3]] 26 set_property IOSTANDARD LVCMOS33 [get_ports out[3]] 27 set_property PACKAGE_PIN V5 [get_ports out[2]] 28 set_property IOSTANDARD LVCMOS33 [get_ports out[2]] 29 set_property PACKAGE_PIN U7 [get_ports out[1]] 30 set_property IOSTANDARD LVCMOS33 [get_ports out[1]] 31 set_property PACKAGE_PIN V7 [get_ports out[0]] 32 set_property IOSTANDARD LVCMOS33 [get_ports out[0]]
