【FPGA学习笔记】VL35 状态机-非重叠的序列检测

设计一个状态机，用来检测序列 10111，要求：

1、进行非重叠检测即101110111 只会被检测通过一次

2、寄存器输出且同步输出结果

注意rst为低电平复位

信号示意图：

波形示意图：

状态机：

`timescale 1ns/1ns
 
module sequence_test1(
    input wire clk  ,
    input wire rst  ,
    input wire data ,
    output reg flag
);
//*************code***********//
    parameter S0=0, S1=1, S2=2, S3=3, S4=4, S5=5;
    reg [2:0] state, nstate;
 
    always@(posedge clk or posedge rst) begin
        if(~rst)
            state <= S0;
        else
            state <= nstate;
    end
     
    always@(*) begin
        if(~rst)
            nstate <= S0;
        else
            case(state)
                S0     : nstate = data? S1: S0;
                S1     : nstate = data? S0: S2;
                S2     : nstate = data? S3: S0;
                S3     : nstate = data? S4: S0;
                S4     : nstate = data? S5: S0;
                S5     : nstate = data? S1: S0;
                default: nstate = S0;
            endcase
    end
     
    always@(*) begin
        if(~rst)
            flag <= 0;
        else
            flag <= state==S5;
    end
//*************code***********//
endmodule