【HDLBits刷题笔记】06 Basic Gates
Exams/m2014 q4h
module top_module ( input in, output out); assign out=in; endmodule
Exams/m2014 q4i
module top_module ( output out); assign out=1'b0; endmodule
Exams/m2014 q4e
module top_module ( input in1, input in2, output out); assign out=!(in1|in2); endmodule
Exams/m2014 q4f
module top_module ( input in1, input in2, output out); assign out=in1&~in2; endmodule
Exams/m2014 q4g
module top_module ( input in1, input in2, input in3, output out); assign out=in3^(~(in1^in2)); endmodule
Gates
搞不懂为啥出这么多这种题.
module top_module( input a, b, output out_and, output out_or, output out_xor, output out_nand, output out_nor, output out_xnor, output out_anotb ); assign out_and=a&b; assign out_or=a|b; assign out_xor = a^b; assign out_nand=~(a&b); assign out_nor=~(a|b); assign out_xnor = ~(a^b); assign out_anotb = a&~b; endmodule
7420
module top_module ( input p1a, p1b, p1c, p1d, output p1y, input p2a, p2b, p2c, p2d, output p2y ); assign p1y=~(p1a&p1b&p1c&p1d); assign p2y=~(p2a&p2b&p2c&p2d); endmodule
Truthtable1
时钟真值表实现组合逻辑,这种时候电路会综合成最小项(与门)之和(或门)的形式。我这里代码使用的是真值表,答案是直接把最小项之和写了出来,综合出的电路应该是一样的。
module top_module( input x3, input x2, input x1, // three inputs output f // one output ); always@(*) begin case({x3,x2,x1}) 3'b000:f=0; 3'b001:f=0; 3'b010:f=1; 3'b011:f=1; 3'b100:f=0; 3'b101:f=1; 3'b110:f=0; 3'b111:f=1; endcase end endmodule
Mt2015 eq2
module top_module ( input [1:0] A, input [1:0] B, output z ); assign z=(A==B)?1'b1:1'b0; endmodule
Mt2015 q4a
module top_module (input x, input y, output z); assign z=(x^y)&x; endmodule
Mt2015 q4b
这题要求看波形得到逻辑表达式,显然该逻辑关系代表同或。
module top_module ( input x, input y, output z ); assign z=~(x^y); endmodule
Mt2015 q4
根据RTL视图写代码。
module top_module (input x, input y, output z); wire z1,z2; A IA1(x,y,z1); B IB1(x,y,z2); assign z=(z1|z2)^(z1&z2); endmodule module A (input x, input y, output z); assign z=(x^y)&x; endmodule module B ( input x, input y, output z ); assign z=~(x^y); endmodule
Ringer
这题也是只要把题目意思翻译成逻辑表达式即可。
module top_module ( input ring, input vibrate_mode, output ringer, // Make sound output motor // Vibrate ); assign ringer=(ring&~vibrate_mode)?1'b1:1'b0; assign motor=(ring&vibrate_mode)?1'b1:1'b0; endmodule
Thermostat
翻译题目意思即可,题目给的答案更简洁:fan = heater | aircon | fan_on;heater = (mode & too_cold);aircon = (~mode & too_hot);。
module top_module ( input too_cold, input too_hot, input mode, input fan_on, output heater, output aircon, output fan ); assign heater=(mode==1'b1&&too_cold == 1'b1)?1'b1:1'b0; assign aircon=(mode==1'b0&&too_hot == 1'b1)?1'b1:1'b0; assign fan=(heater||aircon||fan_on)?1'b1:1'b0; endmodule
Popcount3
我这里直接用的加法实现了,题目用的逻辑实现的,较为复杂:out[0] = (~in[2] & ~in[1] & in[0]) | (~in[2] & in[1] & ~in[0]) | (in[2] & ~in[1] & ~in[0]) | (in[2] & in[1] & in[0]);out[1] = (in[1] & in[0]) | (in[2] & in[0]) | (in[2] & in[1]);
module top_module( input [2:0] in, output [1:0] out ); assign out=in[0]+in[1]+in[2]; endmodule
Gatesv
答案的方法要简洁很多,out_any = in[3:1] | in[2:0];out_both = in[2:0] & in[3:1];out_different = in ^ {in[0], in[3:1]};
module top_module( input [3:0] in, output [2:0] out_both, output [3:1] out_any, output [3:0] out_different ); assign out_both[2:0]={in[3]&in[2],in[2]&in[1],in[1]&in[0]}; assign out_any[3:1]={in[3]|in[2],in[2]|in[1],in[1]|in[0]}; assign out_different[3:0]={in[3]^in[0],in[3]^in[2],in[2]^in[1],in[1]^in[0]}; endmodule
Gatesv100
参考上一题的答案即可。
module top_module( input [99:0] in, output [98:0] out_both, output [99:1] out_any, output [99:0] out_different ); assign out_both=in[98:0]&in[99:1]; assign out_any=in[99:1]|in[98:0]; assign out_different=in^{in[0],in[99:1]}; endmodule