卷积器设计笔记2

经过几天的调试终于有结果了，但是程序还有待优化。调试发现还是基础比较薄弱没有好好的看书，感觉还是要把夏宇闻的书好好看下。在夏宇闻书中写到：“若在同一个时钟的正跳沿下对寄存器组既进行输入又进行输出，很有可能由于门的延迟使输入条件还未确定时，就输出了下一个状态，这种情况会导致逻辑的紊乱。而利用上一个时钟为下一个时钟创造触发条件的方式是安全可靠的。在实际电路的实现中，采取了许多有效的措施来确保成立：1.全局时钟网络布线时尽量使各分支的时钟一致。2.采用平衡树结构，在每一级加入缓冲器，使达到每个触发器时钟端的时钟同步。”

我的程序中的ram_read的状态中，既对ram_output_data和rom_output_data赋值，又对其进行运算，导致数据有个延时。

                ram_read: begin    
                        if (ROM_count <= count3)    begin        
                            RAM_ADDR_R <= count2;
                            ROM_ADDR <= ROM_count;
                            ram_output_data <= ram_output;
                            rom_output_data <= rom_output;
                            da_data_ <= ram_output_data * rom_output_data + da_data_;
                            if (count2 == 0) begin
                                
                            end
                            else begin
                                count2 <= count2 - 1;
                            end
                            ROM_count <= ROM_count + 1;
                            state <= ram_read;
                        end
                        else state <= state_data_output;
                    end
                state_data_output: begin
                        da_data <= da_data_[31:16] + 16'd32767;
                        state <= ram_write;
                    end
                default: state <= ram_idle;
            endcase        
    end    

后来将赋值和运算分两个状态后，数据少了一个延时，但是还是将之前的一个数据计算进去了。又在夏宇闻书中看到用非阻塞赋值是先存到一个隐藏的寄存器里，待下一个时钟来到输出，既第一次计算还是上一次存储的数据，所以我将RAM和ROM的地址做了下缓存之后再给出，结果就正确了。

                ram_write: begin
                        if (ad_clk_pos)
                           begin
                                RAM_ADDR_W <= count1;
                                ram_wr <= 1'b1;    
                                da_data_ <= 32'd0;    
                                count4 <= 16'd0;
                                ROM_count <= 5'd0;
                                ram_output_data <= 16'd0;
                                rom_output_data <= 16'd0;                            
                                ram_data <= ad_data - 16'd32767;
                                state <= ram_count;
                            end
                        end
                ram_count: begin
                            if (count1 == 16'd31)    begin                                    
                                count2 <= count1;
                                count3 <= count1;
                                count1 <= 16'd0;
                            end
                            else    begin
                                count2 <= count1;
                                count3 <= count1;                                    
                                count1 <= count1 + 16'd1;                                                                        
                            end
//                            RAM_ADDR_R <= count2;
//                            ROM_ADDR <= ROM_count;                                                
                            state <= ram_WR_END;
                           end
                ram_WR_END:    begin
                        ram_wr <= 1'b0;
                        state <= ram_wait;
                    end
                ram_wait: begin
                            RAM_ADDR_R <= count2;
                            ROM_ADDR <= ROM_count;
                            state <= ram_read;
                    end
                ram_read: begin    
                        if (ROM_count <= count3)    begin    
                                RAM_ADDR_R <= count2;
                                ROM_ADDR <= ROM_count;
                                state <= ram_dddd;
                        end
                        else state <= state_data_output;
                        
                    end
                ram_dddd: begin
                        if (count4 == 2)    begin
                            count4 <= 16'd0;
                            state <= ram_delay;
                        end
                        else    begin
                            count4 <= count4 + 1;
                            state <= ram_dddd;
                        end    
                    end
                ram_delay:begin
                        ram_output_data <= ram_output;
                        rom_output_data <= rom_output;
                        state <= ram_process;
                    end
                ram_process:begin
                        da_data_ <= ram_output_data * rom_output_data + da_data_;
                        if (count2 == 0) begin
                            
                        end
                        else begin
                            count2 <= count2 - 16'd1;
                        end
                        ROM_count <= ROM_count + 5'd1;
                        state <= ram_read;
                    end
                state_data_output: begin
                        da_data <= da_data_[31:16] + 16'd32767;
                        state <= ram_write;
                    end
                default: state <= ram_idle;
            endcase        
    end    

此图是我改进之后的仿真信号图：

在这几天的调试过程中，遇到了很多小的问题，导致仿真出来的结果和自己预想的总是差了点，发现自己对verilog了解的太少了，还停留在C语言的调试状态下。