1 # -----------------------------------------------------------------------------
2 # Vivado Non-Project Flow
3 # -----------------------------------------------------------------------------
4 set DESIGN [lindex $argv 0]
5
6 # -----------------------------------------------------------------------------
7 config_webtalk -user off
8
9 # -----------------------------------------------------------------------------
10 create_project -in_memory
11
12 # -----------------------------------------------------------------------------
13 proc read_filelist {filelist} {
14 global hdl_list
15 global incdir_list
16 set fp [open $filelist r]
17 while {[gets $fp fname] != -1} {
18 if {[regexp {^//} $fname]} {
19 continue
20 } elseif {[regexp {^\S+\.v} $fname]} {
21 lappend hdl_list $fname
22 } elseif {[regexp {^-v} $fname]} {
23 regsub {^-v} $fname "" fname_sub
24 lappend hdl_list $fname_sub
25 } elseif {[regexp {^\+incdir\+} $fname]} {
26 regsub {^\+incdir\+} $fname "" fname_sub
27 lappend incdir_list $fname_sub
28 }
29 }
30 close $fp
31 }
32
33 # -----------------------------------------------------------------------------
34 set hdl_list ""
35 set incdir_list ""
36 read_filelist "../../rtl/filelist.f"
37
38 set_property verilog_define "SYNTHESIS" [current_fileset]
39 set_property include_dirs $incdir_list [current_fileset]
40 set_property top ${DESIGN} [current_fileset]
41
42 read_verilog $hdl_list
43 #read_ip "../scr/ila_debug.xci"
44 read_xdc "../scr/${DESIGN}.xdc"
45
46 # -----------------------------------------------------------------------------
47 synth_design -top ${DESIGN} -part xc7z020clg400-2
48 write_checkpoint -force ../rpt/${DESIGN}_synth.dcp
49 report_utilization -file ../rpt/${DESIGN}_synth_utilization.rpt
50 report_timing_summary -file ../rpt/${DESIGN}_synth_timing_summary.rpt
51
52 # -----------------------------------------------------------------------------
53 if {[llength [get_debug_cores -quiet]] > 0} {
54 implement_debug_core
55 }
56
57 write_debug_probes ../rpt/${DESIGN}.ltx
58
59 # -----------------------------------------------------------------------------
60 opt_design -directive Explore
61 place_design -directive Explore
62 phys_opt_design -directive Explore
63 write_checkpoint -force ../rpt/${DESIGN}_placed.dcp
64 report_utilization -file ../rpt/${DESIGN}_placed_utilization.rpt
65 report_timing_summary -file ../rpt/${DESIGN}_placed_timing_summary.rpt
66
67 # -----------------------------------------------------------------------------
68 route_design -directive Explore -tns_cleanup
69 phys_opt_design -directive Explore
70 write_checkpoint -force ../rpt/${DESIGN}_routed.dcp
71 report_route_status -file ../rpt/${DESIGN}_routed_status.rpt
72 report_timing_summary -file ../rpt/${DESIGN}_routed_timing_summary.rpt
73
74 # -----------------------------------------------------------------------------
75 write_bitstream -force ../rpt/${DESIGN}.bit
76 write_cfgmem -format bin -interface SPIx1 -size 256 -loadbit "up 0 ../rpt/${DESIGN}.bit" ../rpt/${DESIGN}.bin
