#******************************************************************************
# File : syn_example.tcl
# Author : Lyu Yang
# Date : 2018-12-09
# Description : Design Compiler
#******************************************************************************
sh mkdir -p work
set cache_write work
set cache_read work
define_design_lib WORK -path work
# Library Setup
set search_path {. /smic180/digital/sc/synopsys}
set symbol_library {smic18.sdb}
set target_library {slow.db}
set link_library {* slow.db}
# SVF For Formality
set_svf -off
# Elaborate Design
set DESIGN "design_top"
analyze -format verilog -vcs "-f ../rtl/${DESIGN}.f"
elaborate ${DESIGN}
current_design ${DESIGN}
link
uniquify -force -dont_skip_empty_designs
# Operating Condition
set_operating_conditions -analysis_type on_chip_variation
set_wire_load_model -name smic18_wl10
set_wire_load_mode top
# DRC Rules
set_max_area 0
set_max_fanout 32 [get_designs $DESIGN]
set_max_transition 1.0 [get_designs $DESIGN]
set_max_capacitance 1.0 [get_designs $DESIGN]
# Constraints
set_drive 0.1000 [all_inputs]
set_load 0.0003 [all_outputs]
create_clock -name CCLK_CLK -period 5.0 [get_ports clk]
set_input_delay 1.0 -max -clock {CCLK_CLK} [remove_from_collection [all_inputs] [get_ports clk]]
set_output_delay 1.0 -max -clock {CCLK_CLK} [all_outputs]
set_clock_uncertainty 0.15 -setup [all_clocks]
# Check Design
redirect ../rpt/${DESIGN}_check_design.rpt "check_design"
# Compile Design
compile -scan
# Write Netlist
change_names -rules verilog -hierarchy
write_file -hier -format verilog -output ../rpt/${DESIGN}.syn.v
# Reports
redirect ../rpt/${DESIGN}_timing.rpt "report_timing"
redirect ../rpt/${DESIGN}_area.rpt "report_area -hier"
redirect ../rpt/${DESIGN}_qor.rpt "report_qor -hier"
