RISC-V SBI规范
RISC-V SBI SPEC https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
什么是SBI
RISC-V Supervisor Binary Interface Specification
Mode | RISC-V | ARM |
---|---|---|
Userspace | U-Mode | EL0 |
Kernel | S-Mode | EL1 |
Hpervisor | HS-Mode | EL2 |
Machine | M-Mode(OpenSBI) | S-EL3(ATF) |
Reference
- RISC-V OpenSBI 快速上手 - 泰晓科技 https://tinylab.org/riscv-opensbi-quickstart/