摘要： module lxl(clk,rst,led,sel,dig);input clk,rst;output reg [7:0] led;output reg [5:0] sel;output [7:0] dig;parameter s1=1'b0,s2=1'b1;reg current_state,next_state;parameter T1s=31'd2_0000_000;reg [4:0] t;reg [31:0] cnt,cnt1;wire w;reg clk_out;always @ (posedge clk or negedge rst)if(!rst)beg 阅读全文