摘要： module pwm (clk, write_data, cs, write_n, addr, clr_n, read_data, pwm_out); input clk; input [31:0] write_data; input cs; input write_n; input addr; input clr_n; output [31:0] read_data; output pwm_out; // 定义period和pulse_width寄存器的内容 reg [31:0] period;reg [31:0] pulse_width;reg [31:0] counter;reg off 阅读全文