摘要:
module state(CLOCK,RESET,LED,KEY_UP);input CLOCK,RESET,KEY_UP;output reg [3:0] LED;parameter s1=2'b00,s2=2'b01,s3=2'b10,s4=2'b11;reg [1:0] current_state,next_state;reg t;parameter T1s=23'd2_000_00000;reg [22:0] cnt;always @ (posedge CLOCK or negedge RESET)if(!RESET)begincnt<=0 阅读全文