摘要：
module test(RESET,CLOCK,SEL,DIG,KEY_UP,KEY_DOWN);input RESET,CLOCK,KEY_UP,KEY_DOWN;output reg[5:0] SEL;output reg[7:0] DIG;parameter cnt=32'd2_000_0;reg[31:0] cnt1;reg[3:0] b;wire[3:0] t;always @ (posedge CLOCK or negedge RESET)beginif(!RESET)begincnt1<=0;b<=0;endelse if(cnt1==cnt)beginb&l 阅读全文
摘要：
module test(RESET,CLOCK,SEL,DIG,KEY_UP,KEY_DOWN);input RESET,CLOCK,KEY_UP,KEY_DOWN;output reg[5:0] SEL;output reg[7:0] DIG;parameter cnt=32'd2_000_0;reg[31:0] cnt1;reg b;wire t;always @ (posedge CLOCK or negedge RESET)beginif(!RESET)begincnt1<=0;b<=0;endelse if(cnt1==cnt)beginb<=~b;cnt1 阅读全文