摘要： module test(KEY_UP,SEL,DIG,CLOCK,RESET);input KEY_UP,CLOCK,RESET;output [5:0] SEL;output reg [7:0] DIG;parameter cnt=23'd2_000_000;reg [22:0] cnt1;reg [31:0] count;reg t;wire b;always @ (posedge CLOCK or negedge RESET)beginif(!RESET)t<=1;else if(!KEY_UP)t<=0;else t<=1;endassign b=t;alwa 阅读全文