用verilog编写的PWM控制
module pwm(CLOCK,RESET,LED);
input CLOCK,RESET;
output reg [3:0] LED;
parameter T1s=32'd1_00000;
reg [31:0] t,count;
reg [31:0] w;
///*
always @(posedge CLOCK or negedge RESET)
if(!RESET)
begin
count<=0;
t<=0;
LED[0]<=0;
end
else if(count==T1s)
begin
count<=0;
t<=t+1000;
if(t==T1s)
t<=0;
end
else
begin
count<=count+1;
if(count<t)
LED[0]<=0;
else
LED[0]<=1;
end
//*/
/*
always @(posedge CLOCK or negedge RESET)
if(!RESET)
begin
t<=0;
LED[0]<=0;
end
else if(t==T1s/10)
begin
t<=t+1;
LED[0]<=~LED[0];
end
else if(t==T1s)
t<=0;
else
t<=t;
*/
/*
always @(posedge CLOCK or negedge RESET)
if(!RESET)
LED[0]<=0;
else if(count<t)
LED[0]<=0;
else
LED[0]<=1;
*/
endmodule