基于黑金开发板的秒表verilog hdl程序

module test(RESET,CLOCK,SEL,DIG,KEY_UP,KEY_DOWN);
input RESET,CLOCK,KEY_UP,KEY_DOWN;
output reg[5:0] SEL;
output reg[7:0] DIG;
parameter cnt=32'd2_000_0;
reg[31:0] cnt1;
reg[3:0] b;
wire[3:0] t;
always @ (posedge CLOCK or negedge RESET)
begin
 if(!RESET)
 begin
  cnt1<=0;
  b<=0;
  end
   else if(cnt1==cnt)
    begin
    b<=b+1;
    cnt1<=0;
    if(b>=5)
    b<=0;
    
    end
     else
      begin
      cnt1<=cnt1+1;
      b<=b;
      end
end
assign t=b;
parameter cnt2=32'd5_000_000;
reg[31:0] cnt3;
reg d;
wire din;
always @ (posedge CLOCK or negedge RESET)
begin
 if(!RESET)
  d<=1;
   else if((!KEY_UP)||(!KEY_DOWN))
    d<=0;
     else
      d<=1;
end
assign din=d;
reg[31:0] size;
wire[31:0] sec;
reg[31:0] size1;
wire[31:0] min;
reg[31:0] size2;
wire[31:0] hour;
/*
always @ (posedge CLOCK or negedge RESET)
begin
 if(!RESET)
  size<=0;
   else if(cnt3==cnt2)
    begin
     cnt3<=0;
     if(din==0)
     begin
      if(!KEY_UP)
      begin
      size<=size+1;
      if(size>=59)
      size<=0;
      end
      else if(!KEY_DOWN)
      begin
      size<=size-1;
      if(size<=0)
      size<=59;
      end
      end
    end
    else
    cnt3<=cnt3+1;
end
assign count=size;*/
always @ (posedge CLOCK or negedge RESET)
begin
 if(!RESET)
 begin
 size<=0;
 size1<=0;
 size2<=0;
 end
  else if(cnt3==cnt2)
  begin
   cnt3<=0;
   size<=size+1;
   if(size>=59)
   begin
   size<=0;
   
   size1<=size1+1;
   //size1<=0;
   if(size1>=59)
     begin
      size1<=0;
      size2<=size2+1;
      if(size2>=23)
      size2<=0;
      end
      end
   
   end
    
      
      
  
   else
   begin
    cnt3<=cnt3+1;
    size<=size;
    size1<=size1;
    size2<=size2;
    end
end
assign sec=size;
assign min=size1;
assign hour=size2;
always @ (posedge CLOCK or negedge RESET)
begin
 if(!RESET)
  DIG<=display(3);
   else if(t==0)
   begin
    DIG<=display(ge(sec));
    SEL<=6'hfe;
   end
     else if(t==1)
     begin
      DIG<=display(shi(sec));
      SEL<=6'hfd;
     end
     else if(t==2)
     begin
      DIG<=display(ge(min));
      SEL<=6'b111011;
     end
     else if(t==3)
     begin
      DIG<=display(shi(min));
      SEL<=6'b110111;
     end
     else if(t==4)
     begin
      DIG<=display(ge(hour));
      SEL<=6'b101111;
     end
     else
     begin
      DIG<=display(shi(hour));
      SEL<=6'b011111;
     end
end
function [7:0] display;
input[3:0] key;
case(key)
0: display=8'hc0;
1: display=8'hf9;
2: display=8'ha4;
3: display=8'hb0;
4: display=8'h99;
5: display=8'h92;
6: display=8'h82;
7: display=8'hf8;
8: display=8'h80;
default: display=8'h90;
endcase
endfunction
function[31:0]  shi;
input [31:0] cou;
shi=cou/10;
endfunction
function[31:0]  ge;
input [31:0] cou;
ge=cou%10;
endfunction
endmodule