verilog 实战 与非门

代码在git 你可以直接 sh compile.sh来运行

nandgate.v

//与非门设计
`timescale 1ns/10ps

module nand_gate( 
    input A, 
    input B, 
    output Y );
    assign Y=~(A & B);
endmodule

stimulus_tb.v

//-------testbench of nandgate------------
//与非门
//罗干 2022-05-10

`timescale 1ns/10ps

module  nand_gate_tb;

reg   aa;
reg   bb;
wire  yy;


nand_gate nand_gate (
          .A(aa),
          .B(bb),
          .Y(yy)
           );

initial begin
    $dumpfile("test.vcd");
    $dumpvars(0,nand_gate_tb);
        aa<=0;  bb<=0;
    #10 aa<=1;  bb<=0;
    #10 aa<=0;  bb<=1;
    #10 aa<=1;  bb<=1;
    #10 $stop;
end 
endmodule

#!/bin/bash
echo "开始编译"

iverilog nandgate.v stimulus_tb.v -o nand

#./invet

echo "编译完成"
vvp -n nand -lxt2
echo "生成波形文件"
cp test.vcd wave.lxt
echo "打开波形文件"
gtkwave wave.lxt