verilog 四级 伪随机数发生器

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代码在git
.
目录结构
├── compile.sh
├── random.v
└── stimulus_tb.v

random.v

//2022-05-17
//四级伪随机码发生器


`timescale 1 ns/10 ps 
module m_gen (clk,res,y);

input        clk;
input        res;
output        y;
reg[3:0]     d;       //触发器定义成reg变量;

assign       y=d[0]; 

always@(posedge clk or negedge res)

if (~res) begin 
    d<=4'b1111;  
    end
else begin 

   d[2:0]<=d[3:1];  //右移一位
   d[3]<=d[3]+d[0];

end 


endmodule 

stimulus_tb.v

//-----testbench  of m_gen-----

`timescale 1 ns/10 ps 


module m_gen_tb;

reg        clk,res;

wire        y;
//异名例化

m_gen  m_gen (.clk(clk),
          .res(res),
          .y(y));
 
initial begin
    $dumpfile("test.vcd");
    $dumpvars(0,m_gen_tb);
     

         clk<=0 ;res<=0;
    #17 res<=1;
    # 600 $stop;         
end

always #5 clk=~clk;
 
endmodule

#!/bin/bash
echo "开始编译"

iverilog random.v stimulus_tb.v -o fn

#./invet

echo "编译完成"
vvp -n fn -lxt2
echo "生成波形文件"
cp test.vcd wave.lxt
echo "打开波形文件"
gtkwave wave.lxt