verilog 秒计数器,分频器

.
├── compile.sh
├── sec_count.v
└── stimulus_tb.v

代码在git

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sec_count.v

//2022-05-18 ,罗干
//秒计数器,0-9 循环;

`timescale 1ns/10ps
module s_counter(
                 clk,
		           res,
		           s_num,
                 );
input           clk;
input           res;
output[3:0]     s_num;

reg[24:0]       con_t;  //秒脉冲分频计数器

parameter       frequency_clk=24;  //24MHz

reg             s_pulse ;  //秒脉冲尖;
reg[3:0]        s_num;
always@(posedge clk or negedge res )

   if (~res )begin 
   	con_t<=0;s_pulse<=0;s_num<=0;
   end

   else begin 

        if (con_t==frequency_clk*1000-1)begin
   	     con_t<=0;
   	  end
        else begin 	 
        con_t<=con_t+1;
        end

        if (con_t==0)begin 
        
        s_pulse <=1;	     
        end

        else begin 
        s_pulse <=0;
        end
        
        if (s_pulse) begin 
            
   	      if (s_num==9) begin  
                           		 
               s_num<=0; 
            end 
            else begin 

               s_num <=s_num +1;
            end 
         end 
   end   

endmodule

stimulus_tb.v

//-----testbench  of s_counter-----

`timescale 1 ns/10 ps 


module m_gen_tb;

reg        clk,res;

wire[3:0]        s_num;

s_counter s_counter( .clk(clk),
                     .res(res),
                     .s_num(s_num));
initial begin
    $dumpfile("test.vcd");
    $dumpvars(0,m_gen_tb);
     

         clk<=0 ;res<=0;
    #17 res<=1;
    # 10000000 $stop;         
end

always #5 clk=~clk;
 
endmodule

compile.sh

#!/bin/bash
echo "开始编译"

iverilog sec_count.v stimulus_tb.v -o fn

#./invet

echo "编译完成"
vvp -n fn -lxt2
echo "生成波形文件"
cp test.vcd wave.lxt
echo "打开波形文件"
gtkwave wave.lxt