(笔记)构建基于aemb的sopc系统(二)--硬件相关2
读一下《MicroBlaze Processor Reference Guide》
EDK的各个版本,AEMB可以分别兼容EDK32,EDK62和EDK63。
Aemb的体系结构
MicroBlaze Core Block Diagram
MicroBlaze uses Big-Endian, bit-reversed format to represent data.
32个32-bit通用功能寄存器,2个32-bit特殊功能寄存器。
32个32-bit 的General Purpose Register
Special Purpose Registers:
Ø Program Counter (PC)
Ø Machine Status Register (MSR)
Ø Exception Address Register (EAR)
Ø Exception Status Register (ESR)
Harvardmemory architecture:
Ø Instruction and data accesses are done in separate address spaces. Each address space has a 32 bit range.
Ø The instruction and data memory ranges can be made to overlap by mapping them both to the same physical memory.
Ø Does not separate between data accesses to I/O and memory
Reset, Interrupts, Exceptions and Break
Vectors and Return Address Register File Location
Fast Simplex Link (FSL)
MicroBlaze contains eight Fast Simplex Link (FSL) interfaces, each consisting of one input
and one output port. The FSL channels are dedicated uni-directional point-to-point data
streaming interfaces.
FSL是做什么用的,Hardware Acceleration?类似于NiosII的Custom Instructions?FSL provides a fast non-arbitrated streaming communication mechanism
FSL used with HW accelerated function fx
应该可以不接
后记:得接,不然仿真时核起不来。
MicroBlaze Application Binary Interface
Register usage conventions. The architecture for MicroBlaze defines 32 general purpose registers (GPRs). These registers are classified as volatile, non-volatile and dedicated.
Interrupt and Exception Handling
MicroBlaze allows exception and interrupt handler routines to be located at any address location addressable using 32 bits. The user exception handler code starts with the label _exception_handler, the hardware exception handler starts with _hw_exception_handler, while the interrupt handler code starts with the label _interrupt_handler.
In the current MicroBlaze system, there are dummy routines for interrupt and exception handling, which you can change. In order to override these routines and link your interrupt and exception handlers, you must define the interrupt handler code with an attribute interrupt_handler.