（笔记）如何在Quartus II中设置Virtual pin（Make All Pins Virtual）

If you use a modular LogicLock? design flow in your project, you may choose to make all the I/O pins in a module virtual I/O pins as a way to easily import the module in a top-level design. Also, if you want to compile an IP core to see how many resources it uses but it uses too many pins for your target device, making the pins virtual may allow the core to fit.
The following simple procedure makes all pins in your design virtual I/O pins. First, the design is synthesized to determine which nodes are pins. Next, a collection of name IDs is set to correspond to the pins in the design, then a VIRTUAL_PIN assignment is applied to every pin.
Finally, the export_assignments command writes all new assignments to the project's Quartus? II Settings File (.qsf).
The example uses the get_names and get_name_info commands, which are available beginning in version 4.0 of the Quartus II software (version 2.0 of the ::quartus::project package). Refer to the last example on this page for code that will work beginning with version 3.0 of the Quartus II software, and has more advanced capabilities.

load_package flow
proc make_all_pins_virtual {} {
    execute_module -tool map
    set name_ids [get_names -filter * -node_type pin]
    foreach_in_collection name_id $name_ids {
        set pin_name [get_name_info -info full_path $name_id]
        post_message "Making VIRTUAL_PIN assignment to $pin_name"
        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
    }
    export_assignments
}
将以下代码
    execute_module -tool map
    set name_ids [get_names -filter * -node_type pin]
    foreach_in_collection name_id $name_ids {
        set pin_name [get_name_info -info full_path $name_id]
        post_message "Making VIRTUAL_PIN assignment to $pin_name"
        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
    }
    export_assignments
保存为.tcl格式的文件，在Quartus II -> Tools -> Tcl Scripts中选中所保存的tcl文件，点击run
 
或者参考以下文章
使用Virtual Pin约束IP的片上信号
http://eda.jimmystone.cn/
by Jimmy Stone
   为了验证FPGA工程中的某个IP的功能和时序的正确性，常常需要对其单独进行验证，但是这些IP模块通常都与内部的众多信号相连（如系统总线，中断信号线等），
往往一个模块的对外接口会多达几百个，对其单独仿真的话，可能会对目标FPGA造成IO资源不足的情况。即使IO资源满足，当众多内部信号变成IO信号时，模块内部的
信号将增加额外的IO延时，增加了时序约束的复杂度。
   为了避免以上情况的出现，常常使用Virtual Pin对非IO引脚的信号进行约束，经过约束的信号，综合布线器将不对其分配IO资源。
   具体方法如下：
   在Quartus II中Assignments->Assignment Editor，在To列下添加IP核的片内接口，将Assignment Name设置为Virtual Pin，将Value设置为On，
Enabled 设置为Yes， 这样设置为Virtual Pin 就不会占用FPGA的IO资源，而且时序仿真不会增加额外的延时，更加准确。