About external memory interface of DDR2
1. Cyclone IV data pins for external memory interfaces are called D for write data, Q for
read data, or DQ for shared read and write data pins. The read-data strobes or read
clocks are called DQS pins.
2. Cyclone IV devices do not support differential strobe pins, which is an optional
feature in the DDR2 SDRAM device.
3. The auto-calibration feature of ALTMEMPHY provides ease-of-use by optimizing clock
phases and frequencies across process, voltage, and temperature (PVT) variations.
4. All I/O banks in Cyclone IV devices can support DQ and DQS signals with DQ-bus
modes of ×8, ×9, ×16, ×18, ×32, and ×36 except Cyclone IV GX devices that do not
support left I/O bank interface. DDR2 and DDR SDRAM interfaces use ×8 mode DQS
group regardless of the interface width. For a wider interface, you can use multiple ×8
DQ groups to achieve the desired width requirement.（注：这里的意思估计是如果要用更大
的总线宽度，那么宽度一定要是8的倍数）
5. DM pins are only required when writing to DDR2 and DDR SDRAM devices.
Each group of DQS and DQ signals has one DM pin. Similar to the DQ output signals, the DM signals are
clocked by the -90° shifted clock.
In Cyclone IV devices, the DM pins are preassigned in the device pinouts. The
Quartus II Fitter treats the DQ and DM pins in a DQS group equally for placement
purposes. The preassigned DQ and DM pins are the preferred pins to use.
6. The address signals and the control or command signals are typically sent at a single
data rate. You can use any of the user I/O pins on all I/O banks of Cyclone IV devices
to generate the address and control or command signals to the memory device
7. DQS pins are listed in the Cyclone IV pin tables as DQSXY, in which X indicates the
DQS grouping number and Y indicates whether the group is located on the top (T),
bottom (B), or right (R) side of the device. Similarly, the corresponding DQ pins are
marked as DQXY, in which the X denotes the DQ grouping number and Y denotes
whether the group is located on the top (T), bottom (B), or right (R) side of the device.
For example, DQS2T indicates a DQS pin belonging to group 2, located on the top side
of the device. Similarly, the DQ pins belonging to that group is shown as DQ2T.
(注：关于这一点可以参考具体芯片的pin_out file)
8. You may also share the PLL static clocks for multiple ALTMEMPHY interface,
provided the controllers are on the same side or adjacent side of the device and
running at the same memory clock.
9. DQS (data strobe or data clock) and DQ (data) pins are listed in the device
pin tables and fixed at specific locations in the device. You must adhere to these pin
locations as these locations are optimized in routing to minimize skew and maximize
margin.
10. Assign any address pins to any user I/O pin. To minimize skew within the address
pin group, you should assign the address and command pins in the same bank or
side of the device.
11. Cyclone III and Cyclone IV devices do not support differential DQS signaling.
DDR3 SDRAM mandates differential DQS signaling.
12. mem_clk[0] and mem_clk_n[0] cannot be placed in the same row or column pad group
as any of the DQ pins.
（注：这里的意思是mem_clk[0]和mem_clk_n[0]不能与任何一个DQ pins的X,Y坐标都一样，不然就会
有警告提示。）
13.
Problem
If I am using voltage referenced I/O standards in Cyclone -series devices, can any of the VREF pins be used
as I/O pins in an I/O bank containing voltage referenced input pins?
Solution
Yes, in Cyclone® - series devices you may be able to use some VREF pins as I/O pins in I/O banks containing voltage referenced input pins. The VREF pins are the voltage reference for a VREF group segment, the VREF pins for segments not using voltage referenced input pins within the same I/O bank can be used as regular I/O pins.For example, if you have SSTL 2 Class II input pins in I/O bank 1 and they are all placed in the VREFB1N0 group, then the VREFB1N0 pin will need to be powered with 1.25V to support the SSTL 2 input standard. If the remaining VREFB1N[x] groups (if available for your device) do not have voltage referenced input pins, then the remaining VREFB1N[x] pins (if available for your device) can be used as I/O pins.
If you are using multiple VREF groups within the same I/O bank, the VREF pins for each group must be connected to the same voltage level.
To understand I/O pin placement with respect to VREF groups, you can refer to the Quartus® II software Pin Planner or the device pin-out file.
