单片机——led应用（一）
原理图如下
7脚低，8脚1.4v-0,2脚为0；7脚低，8脚2.4v-5v，2脚高，3脚6脚交替闪烁；
7脚高，8脚0.7v-0v，1脚输出高；7脚高，8脚0.8v-5v，1脚输出低。
8位单片机项目合作联系我：18665321219
/* ========================================================================= * Project: ADC_Polling(eight times average) * File: main.c * Description: ADC Convert With Polling AIN0 or Internal 1/4 VDD eight times then calculate average. * * 1. Set ADC clock frequency is 250KHz , Sample pulse width is 1 ADC clock, * ADC conversion time = (1+12+2)*4us = 60us , ADC conversion rate = 1/60us = 16.6KHz * 2. Poll one of PA0(AIN0) or internal 1/4 VDD as ADC analog input eight times then calculate average. * 3. Store AIN0 channel ADC convert result bit11~ bit0 to RAM "R_AIN0_DATA[11:0]" * 4. Store internal 1/4VDD channel ADC convert result bit11~ bit0 to RAM "R_Quarter_VDD_DATA[11:0]" * Author: JasonLee * Version: V1.1 * Date: 2018.8.30 =========================================================================*/ #include <ny8.h> #include "ny8_constant.h" #include <stdint.h> unsigned int R_AIN0_DATA; unsigned char R_AIN0_DATA_LB; unsigned int R_Quarter_VDD_DATA; unsigned char R_Quarter_VDD_DATA_LB; volatile unsigned char ledcnt; volatile unsigned char fledflg; volatile unsigned char prestate; volatile unsigned char curstate; volatile unsigned int advalue; unsigned char tim_flg; unsigned char outmode; unsigned char cycount = 0; unsigned int cy1count = 0; unsigned int cy2count = 0; unsigned char lockmode = 0; #define UPDATE_REG(x) __asm__("MOVR _" #x ",F") void F_AIN0_Convert(char); //void F_Quarter_VDD_Convert(char); void F_wait_eoc(void); void delay(int); void isr_hw(void) __interrupt(0) { if(INTFbits.T1IF) { tim_flg = 1; INTFbits.T1IF = 0; } } void main(void) { DISI(); //----- Initial GPIO----- IOSTB = C_PB3_Input; // Set PortB as input por PORTBbits.PB3 = 1; // PortB3 Data Register = 1 ，AIN8 //IOSTA = C_PA5_Input ; // PA5 INPUT ,OTHER OUTPUT IOSTA = C_PA5_Input | C_PA3_Input ; // PA5 INPUT ,OTHER OUTPUT //PORTAbits.PA3 = 1; // PORTAbits.PA4 = 0; PORTAbits.PA7 = 0; //INTE = 0x00; // INTE = 0x00 //------------INITIAL TIM1------------------40MS pcs TMRH = 0X10; //1/(4/2)*256*312 = 40 MS TMR1 = 0x38; // T1CR1 = C_TMR1_Reload | C_TMR1_En; //自动重载 T1CR2 = C_TMR1_ClkSrc_Inst | C_PS1_Div256 ; //指令时钟 INTE = INTE | C_INT_TMR1; //使能定时器中断 INTF = 0; //清除中断标志 //----- Initial ADC----- ADMD = C_ADC_CH_Dis | C_ADC_PB3 ; // Enable ADC power, Disable global ADC input channel, Select PB3 pad as ADC input (SFR "ADMD") //----- ADC high reference voltage source select----- ADVREFH = C_Vrefh_VDD; // ADC reference high voltage is supplied by VDD //----- ADC clock frequency select---------------------------- ADR = C_Ckl_Div8; // ADC clock=Fcpu/8, Clear ADIF, disable ADC interrupt //----- ADC Sampling pulse width select------------- ADCR = C_Sample_1clk | C_12BIT | C_PB3_AIN8 ; // Sample pulse width=1 adc clock, ADC select 12-bit conversion,PB ADC input ( Note: ADC clock freq. must be equal or less than 500KHz) //ADCR = C_Sample_1clk | C_12BIT ; //-------------------------------------------------- //PACON = C_PA3_AIN3; ADMDbits.GCHS = 1; // Enable global ADC channel (SFR "ADMD") ADMDbits.ADEN = 1; delay(50); // Delay 0.56ms(Instruction clock=4MHz/2T) for waiting ADC stable //-------------initial value------------- ledcnt = 0; fledflg = 0; prestate = 0; curstate = 0; ENI(); while(1) { CLRWDT(); // Clear WatchDog R_AIN0_DATA=R_AIN0_DATA_LB=R_Quarter_VDD_DATA=R_Quarter_VDD_DATA_LB=0x00; //DISI(); F_AIN0_Convert(8); // execute AIN0 ADC converting 8 times //ENI(); R_AIN0_DATA <<= 4; // R_AIN0_DATA shift left 4 bit R_AIN0_DATA_LB &= 0xF0; // Only get Bit7~4 R_AIN0_DATA += R_AIN0_DATA_LB; // R_AIN0_DATA + R_AIN0_DATA_LB R_AIN0_DATA >>=3; // R_AIN0_DATA divided 8 advalue = R_AIN0_DATA; //prestate = curstate; if(PORTAbits.PA5 == 1) { if(advalue > 0x022f ) //0.0.36/5*4096 = 656(0x0290) { curstate = 2; } else if(advalue < 0x00f8) //0.0.29/5*4096 = 573(0x0230) { curstate = 1; } } else { if(advalue > 0x0c1f) //2.5/5*4096 = 2294(0x08f6) { curstate = 4; } else if(advalue < 0x00f8) //0.0.29/5*4096 = 573(0x0230) { curstate = 3; } } if(tim_flg) //40ms { if(prestate == curstate) { //cycount++; cycount++; if((cycount == 2)&&(lockmode == 0 )) { if(curstate == 1) { outmode = 1; } else if(curstate == 2) { outmode = 2; } else if(curstate == 3) { outmode = 3; } else if((curstate == 4)&&(outmode != 3 )) { outmode = 4; } lockmode = 1; } } else { prestate = curstate; cycount = 0; lockmode = 0; } if(outmode == 3) { cy1count++; if(curstate == 3) { cy2count ++; } else { cy2count = 0; } if(cy1count == 875) { if(cy2count == 875) { outmode = 3; cy2count = 0; cy1count = 0; } else { outmode = 4; } } } else //qiehuang dao mode_1/2 { cy2count = 0; cy1count = 0; } if(fledflg) { ledcnt++; switch(ledcnt) { case 0x3: PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x4: PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x5: case 0x6: PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x7: case 0x8: PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x9: case 0xa: PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0xb: case 0xc: PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0xd: case 0xe: PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0xf: case 0x10: PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x11: case 0x12: PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x13: case 0x14: PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x15: case 0x16: case 0x17: PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x18: case 0x19: PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x1a: case 0x1b: PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x1c: case 0x1d:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x1e: case 0x1f:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x20: case 0x21:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x22: case 0x23:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x24: case 0x25:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x26:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x27:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x28:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x29:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x2a:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x2b:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x2c:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x2d:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x2e:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x2f:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x30:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x31:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x32:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x33:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x34:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x35:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x36:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x37:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x38:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x39:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x3a:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x3b:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x3c:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x3d:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x3e:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x3f:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x40:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x41:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x42:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x43:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x44:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x45:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x46:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x47:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x48:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x49:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x4a:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x4b:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x4c:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x4d:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x4e:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x4f:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x50:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x51:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x52:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x53:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x54:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x55:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x56:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x57:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x58:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x59:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x5a:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x5b:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x5c:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x5d:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x5e:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x5f:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x60:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x61:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x62:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x63:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x64:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x65:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x66:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x67:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x68:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x69:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x6a:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x6b:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x6c:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x6d:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x6f:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x70:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x71:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x72:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x73:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x74:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x75:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x76:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x77:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x78:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x79:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x7a:PORTAbits.PA4=1;PORTAbits.PA7=0; break; case 0x7b:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x7c:PORTAbits.PA4=0;PORTAbits.PA7=1; break; case 0x7d:PORTAbits.PA4=0;PORTAbits.PA7=0; break; case 0x7e:ledcnt=2; PORTAbits.PA4=0;PORTAbits.PA7=0; break; default:break; } } tim_flg = 0; } if(outmode == 1 ) //0.7/5*1024 = 573(0x0230) { fledflg = 0; PORTAbits.PA4=0; PORTAbits.PA7=0; PORTAbits.PA2 = 0; PORTAbits.PA0 = 1; } else if(outmode == 2) //0.8/5*4096 = 656(0x0290) { fledflg = 0; PORTAbits.PA4=0; PORTAbits.PA7=0; PORTAbits.PA2 = 0; PORTAbits.PA0 = 0; } else if(outmode == 3 ) //0.7/5*1024 = 573(0x0230) { PORTAbits.PA0 = 0; PORTAbits.PA2 = 1; if(fledflg == 0) { fledflg = 1; ledcnt = 2; } } else if(outmode == 4) //2.8/5*1024 = 2294(0x08f6) { PORTAbits.PA4=0; PORTAbits.PA7=0; fledflg = 0; PORTAbits.PA0 = 0; PORTAbits.PA2 = 0; } } } //----- Sub-Routine ----- void F_AIN0_Convert(char count) { char i; ADMD = 0x90 | C_ADC_PB3; // Select AIN0(PA0) pad as ADC input CLRWDT(); for(i=1;i<=count;i++) { ADMDbits.START = 1; // Start a ADC conversion session F_wait_eoc(); // Wait for ADC conversion complete R_AIN0_DATA_LB += ( 0x0F & ADR); R_AIN0_DATA += ADD; } } /************************************ void F_Quarter_VDD_Convert(char count) { char i; ADMD = 0x90 | C_Quarter_VDD; // Select internal 1/4VDD as ADC input for(i=1;i<=count;i++) { ADMDbits.START = 1; // Start a ADC conversion session F_wait_eoc(); // Wait for ADC conversion complete R_Quarter_VDD_DATA_LB += ( 0x0F & ADR); R_Quarter_VDD_DATA += ADD; } } **************************************/ void F_wait_eoc(void) { while(ADMDbits.EOC==0) ; } void delay(int count) { int i; for(i=1;i<=count;i++) ; }
