verilog常见错误列表
Error/Warning 来源:https://hdlbits.01xz.net/wiki/ 题目:
1、Quartus Warning 10235:
Warning (10235): Verilog HDL Always Construct warning at FM_mod.v(23): variable "carry_freq" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning原因:由于always过程块敏感列表中未完全包含过程块中使用的所有变量;
常见来源:常见于组合逻辑的always过程块中;
解决方法:将always过程块中的敏感列表改为 ‘ * ’ | 将敏感列表改为边沿触发;
2、逻辑表达式中的括号:
正确:
module fadd_correct(
input a, b, cin,
output cout, sum );
assign sum = a ^ b ^ cin;
assign cout = (a & b) | ((a ^ b) & cin);
endmodule
错误:
module fadd_wrong(
input a, b, cin,
output cout, sum );
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a ^ b & cin);
endmodule