关于place:909 的问题解决 --DDR3 调试记录
使用MIG3.92 双控制器 在V6芯片上调试的时候出现以下问题：
Place:909 - Regional Clock Net "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" cannot possibly be routed to component "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_odelay_dm" (placed in clock region "CLOCKREGIONP_X1Y2"), since it is too far away from source BUFR "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" (placed in clock region "CLOCKREGION_X1Y4"). The situation may be caused by user constraints, or the complexity of the design. Constraining the components related to the regional clock properly may guide the tool to find a solution. To debug your design with partially routed results, please allow map/placer to finish the execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1). Place:909 - Regional Clock Net "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" cannot possibly be routed to component "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[6].u_phy_dm_iob/u_odelay_dm" (placed in clock region "CLOCKREGIONP_X1Y2"), since it is too far away from source BUFR "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" (placed in clock region "CLOCKREGION_X1Y4"). The situation may be caused by user constraints, or the complexity of the design. Constraining the components related to the regional clock properly may guide the tool to find a solution. To debug your design with partially routed results, please allow map/placer to finish the execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1). Place:909 - Regional Clock Net "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" cannot possibly be routed to component "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[5].u_phy_dm_iob/u_odelay_dm" (placed in clock region "CLOCKREGIONP_X1Y2"), since it is too far away from source BUFR "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" (placed in clock region "CLOCKREGION_X1Y4"). The situation may be caused by user constraints, or the complexity of the design. Constraining the components related to the regional clock properly may guide the tool to find a solution. To debug your design with partially routed results, please allow map/placer to finish the execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1). Place:909 - Regional Clock Net "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" cannot possibly be routed to component "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_iob/u_odelay_dm" (placed in clock region "CLOCKREGIONP_X1Y2"), since it is too far away from source BUFR "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" (placed in clock region "CLOCKREGION_X1Y4"). The situation may be caused by user constraints, or the complexity of the design. Constraining the components related to the regional clock properly may guide the tool to find a solution. To debug your design with partially routed results, please allow map/placer to finish the execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1). Place:909 - Regional Clock Net "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<1>" cannot possibly be routed to component "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[3].u_phy_dm_iob/u_odelay_dm" (placed in clock region "CLOCKREGIONP_X1Y2"), since it is too far away from source BUFR "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" (placed in clock region "CLOCKREGION_X1Y4"). The situation may be caused by user constraints, or the complexity of the design. Constraining the components related to the regional clock properly may guide the tool to find a solution. To debug your design with partially routed results, please allow map/placer to finish the execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1). Place:909 - Regional Clock Net "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" cannot possibly be routed to component "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[1].u_phy_dm_iob/u_odelay_dm" (placed in clock region "CLOCKREGIONP_X1Y2"), since it is too far away from source BUFR "i_MigDoubleInterface/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" (placed in clock region "CLOCKREGION_X0Y4"). The situation may be caused by user constraints, or the complexity of the design. Constraining the components related to the regional clock properly may guide the tool to find a solution. To debug your design with partially routed results, please allow map/placer to finish the execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).
个人认为可能时时序方面的问题，但是新手对时序不是很了解，不知道如何解决，在xilinx官网查找相关问题后发现有一个解答。
http://www.xilinx.com/support/answers/40977.html
在最后有一个关于MIG的说明，按照上述方法，重新生成IP核后，问题解决。（因为之前直接更改了ucf文件，所以可能在这出现了问题。）
