verilog forloop/generate

1.verilog for loop实现全加器

// Design for a half-adder
module ha ( input   a, b,
            output  sum, cout);
 
  assign sum  = a ^ b;
  assign cout = a & b;
endmodule
 
// A top level design that contains N instances of half adder
module my_design 
  #(parameter N=4) 
    (  input [N-1:0] a, b,
      output [N-1:0] sum, cout);
 
  // Declare a temporary loop variable to be used during
  // generation and won't be available during simulation
  genvar i;
 
  // Generate for loop to instantiate N times
  generate 
    for (i = 0; i < N; i = i + 1) begin
          ha u0 (a[i], b[i], sum[i], cout[i]);
    end
  endgenerate
endmodule
 

2.verilog generate 实现不同的实现方式的选择？

// Top Level Design: Use a parameter to choose either one
module my_design (  input a, b, sel,
               output out);
  parameter USE_CASE = 0;
 
  // Use a "generate" block to instantiate either mux_case
  // or mux_assign using an if else construct with generate
  generate
    if (USE_CASE) 
      mux_case mc (.a(a), .b(b), .sel(sel), .out(out));
    else
      mux_assign ma (.a(a), .b(b), .sel(sel), .out(out));
  endgenerate
 
endmodule