用脚本进行Innovus设计

版本 日期 说明
V0 2024/06/26 初版

1. 简介

本文针对的情况是，将sdc综合输出的结果输入给Innovus完成布局布线。

2. 数字电路模块设计

2.1. Innovus用到的文件

2.1.1. 必须用到的

  • .lef：工艺文件，往往包含tech lef（工艺叠层的定义）和macro lef（数字单元的定义），有时候是分成两个文件的，这样的话tech lef必须在前
  • MMMC.tcl：一个特殊的Multi-Mode Multi-Corner tcl，描述工艺对应的库和工艺角
  • .v：综合后网表verilog
  • .map：输出gds时使用的工艺层映射关系

2.1.2. 可以用到的

  • .globals：import design相关的设置
  • .fp：floorplan信息
  • .io：io pin信息

2.1.3. 输出文件

  • .gds：版图
  • .sdf：布局布线后的延时信息
  • .v：布局布线后网表

2.2. 数字模块设计流程

  1. Import Design
  2. Floorplan
    • Specify Floorplan
    • Cut Core Row/Cut Rectlinear
    • Relative Floorplan
    • Halo
    • Blockage
  3. Power
    • Connect Global Nets
    • Power Ring
    • SRoute
    • Power Stripe
    • Well Tap
    • Power Pin
  4. Pin
    • Edit Pin(.io or .tcl)
  5. Place & Route
    • PR before CTS
      • Standard Cell
      • ECO Pre-CTS(Recursive)
    • CTS
      • CTS
    • PR after CTS
      • ECO Post-CTS(Recursive)
      • Tie Cell
    • PR route
      • Nano Route
    • PR post route
      • ECO Post-Route
      • Physical Filler
      • Metal Fill
  6. Verify
    • Verify Geometry
    • Verify Connectivity
  7. Export Outputs
    • Export Power Netlist
    • Export No-Power Netlist
    • Export SDF
    • Export GDS

以上步骤仅供参考。

我把Pin放在Power之后的理由是：Power Ring有可能使得Pin放不下。修改Pin相对麻烦，所以先做Power。

PR步骤又被拆成若干步，这样可以更频繁地检查结果，不对的话及时回退。

在后面叙述的脚本中，以上步骤都将用脚本完成，每完成一个阶段就保存一次，方便快速修改。以上步骤中斜体表示按需插入的步骤，并不总是需要。

2.3. 脚本

脚本中重要的步骤用注释加以解释。

即使使用脚本，也不妨打开GUI，在Innovus运行过程中GUI是无法显示的，但是一步做完后可以停一下看一下GUI。

2.3.1. 第一步：Import design

### Initialize innovus
setMultiCpuUsage -localCpu 16 -verbose
source param/inn_cof.globals;#import .globals for initiating
init_design

saveDesign dbs/import.enc -compress;#save innovus dbs

2.3.2. 第二步：Floorplan(FP)

set TOP_NAME xxx;#change your topmodule name
restoreDesign dbs/import.enc.dat $TOP_NAME;#import innovus dbs

setDrawView fplan;#change to fp view in GUI

#------------------------------------------
# Specify floorplan
#------------------------------------------

# Specify floorplan by core size(-s) or by die size(-d)
set FP_W 500    ;# Width
set FP_H 5.04   ;# Height = 5.04 * n
set DIST 10     ;# Core to IO distance
floorPlan -s $FP_W $FP_H $DIST $DIST $DIST $DIST

#------------------------------------------
# Relative floorplan
#------------------------------------------

#------------------------------------------
# Place halo
#------------------------------------------

#------------------------------------------
# Place blockage
#------------------------------------------

### Following are blockage tcl commands
#createPlaceBlockage -box {x1 y1 x2 y2} -type hard
#createRouteBlk -box {x1 y1 x2 y2} -layer {M1 M2 M3}|all
#createPinBlkg -area {x1 y1 x2 y2} -layer {M1 M2 M3}|all

#------------------------------------------
# Save
#------------------------------------------

saveFPlan param/${TOP_NAME}.fp
saveDesign dbs/fp.enc -compress

2.3.3. 第三步：Power

set TOP_NAME xxx
restoreDesign dbs/fp.enc.dat $TOP_NAME

#------------------------------------------
# Global Nets
#------------------------------------------

globalNetConnect VDD -type pgpin -pin VDD -inst *
globalNetConnect VSS -type pgpin -pin VSS -inst *
### Do these only when it is well tap tech, such as SMIC
#globalNetConnect VDD -type pgpin -pin VNW -inst * 
#globalNetConnect VSS -type pgpin -pin VPW -inst *
globalNetConnect VDD -type tiehi -inst *
globalNetConnect VSS -type tielo -inst *
applyGlobalNets

#------------------------------------------
# Ring
#------------------------------------------

addRing \
  -skip_via_on_wire_shape Noshape \
  -skip_via_on_pin Standardcell \
  -jog_distance 0.66 \
  -threshold 0.66 \
  -nets {VDD VSS} \
  -follow io \
  -stacked_via_bottom_layer METAL1 \
  -stacked_via_top_layer METAL6 \
  -type core_rings \
    -layer {bottom METAL1 top METAL1 right METAL2 left METAL2} \
    -width 0.44 \
    -spacing 0.46 \
    -offset 0.66
### offset : distance from outer ring outside edge to io boundary
### spacing : space between two rings

#------------------------------------------
# SRoute(horizontal power rail)
#------------------------------------------

sroute \
  -connect { blockPin padPin padRing corePin floatingStripe } \
  -layerChangeRange { METAL1 METAL6 } \
  -blockPinTarget { nearestTarget } \
  -padPinPortConnect { allPort oneGeom } \
  -padPinTarget { nearestTarget } \
  -corePinTarget { firstAfterRowEnd } \
  -floatingStripeTarget { blockring padring ring stripe ringpin blockpin followpin } \
  -deleteExistingRoutes \
  -allowJogging 1 \
  -crossoverViaLayerRange { METAL1 METAL6 } \
  -nets { VDD VSS } \
  -allowLayerChange 1 \
  -blockPin useLef \
  -targetViaLayerRange { METAL1 METAL6 }

#------------------------------------------
# Stripe(vertical power rail)
#------------------------------------------

### Set the following mode will tap rail to power ring
### and totally remove antennas on vertical power rails

setAddStripeMode \
  -extend_to_closest_target ring \
  -extend_to_first_ring 1

addStripe \
  -skip_via_on_wire_shape Noshape \
  -block_ring_bottom_layer_limit METAL1 \
  -block_ring_top_layer_limit METAL6 \
  -max_same_layer_jog_length 0.88 \
  -padcore_ring_bottom_layer_limit METAL1 \
  -padcore_ring_top_layer_limit METAL6 \
  -skip_via_on_pin Standardcell \
  -stacked_via_bottom_layer METAL1 \
  -stacked_via_top_layer METAL6 \
  -nets {VDD VSS} \
    -spacing 10 \
    -set_to_set_distance 100 \
    -merge_stripes_value 0.66 \
    -layer METAL6 \
    -width 1
### set_to_set_distance : space of two power stripe sets
### spacing : space of two power stripes of identical set
###   (one connected to VDD, the other connected to VSS)

#------------------------------------------
# Well Tap
#------------------------------------------

### Do this only when the tech is well tap, such as SMIC
#addWellTap \
#  -cell FILLTIEHD \
#  -cellInterval 40 \
#  -checkerBoard \
#  -prefix WT
### checkerboard pattern is better because it needs less wt cells

#------------------------------------------
# Save
#------------------------------------------

saveDesign dbs/power.enc -compress

2.3.4. 第三步：Pin

有两种方式，使用 .io或者使用tcl命令来进行。

使用IO：

set TOP_NAME xxx
restoreDesign dbs/power.enc.dat $TOP_NAME

#------------------------------------------
# Place Pins via IO File
#------------------------------------------

loadIoFile ./param/pin.io

#------------------------------------------
# Save
#------------------------------------------

saveDesign dbs/pin.enc -compress

或者使用tcl：

set TOP_NAME xxx
restoreDesign dbs/power.enc.dat $TOP_NAME

#------------------------------------------
# Place Pins via TCL commands
#------------------------------------------

setPinAssignMode -pinEditInBatch true

### Assign 1-bit pins
editPin -fixedPin \
        -fixOverlap 1 \
        -pinWidth 0.44 \
        -pinDepth 0.44 \
        -snap MGRID \
        -global_location \
          -layer {layerId | layerIdList} \
          -side {Top | Bottom | Left | Right} \
          -assign <x> <y> \
          -pin {{name1} {name2}}
### pinWidth & pinDepth : size of pin metal
### assign : coordinate of pin
### pin : typically only include one pin name,
###       if you want to locate different pins,
###       just use several commands!


### Spread bus pins
## For side = right/bottom direction is counterclockwise
## For side = left/top direction is clockwise
editPin -fixedPin \
        -fixOverlap 1 \
        -pinWidth 0.44 \
        -pinDepth 0.44 \
        -snap MGRID \
        -global_location \
        -unit MICRON \
          -layer {layerId | layerIdList} \
          -side {Top | Bottom | Left | Right} \
          -spreadDirection {clockwise counterclockwise} \
          -spreadType start \
          -start <x> <y> \
          -spacing <spacing>\
          -pin {{name1} {name2}}

#------------------------------------------
# Save
#------------------------------------------

saveDesign dbs/pin.enc -compress

值得指出的是，这可能是是命令中最复杂的一步。为了完成放置pin的目标，有可能需要结合其他tcl语句使用，比如for语句等，请灵活使用。

如果将布置Pin时候的距离、坐标等都设成与数字模块总尺寸相关的参数，那么即使后来需要修改整个模块的尺寸，在这一步也只需要修改参数值就可以了，Pin放置的语句基本不用修改，可以成比例放缩。这个习惯会使得返工迭代时效率高很多。

2.3.5. 第四步：PR-Pre CTS

set TOP_NAME xxx
restoreDesign dbs/pin.enc.dat $TOP_NAME

#------------------------------------------
# Place std cell
#------------------------------------------

setPlaceMode -fp false
placeDesign
deleteTrialRoute
### Delete trial route so you clearly see what
###  has actually been placed and connected.

#------------------------------------------
# ECO preCTS
#------------------------------------------

### Opt for twice, normal and incremental
setOptMode -fixCap true -fixTran true -fixFanoutLoad false
optDesign -preCTS -outDir report/ECO_pre_CTS
optDesign -preCTS -incr -outDir report/ECO_pre_CTS_incr
deleteTrialRoute

#------------------------------------------
# Save
#------------------------------------------

saveDesign dbs/pr_pre.enc -compress

2.3.6. 第五步：PR-CTS

set TOP_NAME xxx
restoreDesign dbs/pr_pre.enc.dat $TOP_NAME

setDrawView place

#------------------------------------------
# CTS
#------------------------------------------

setCTSMode -engine ck
createClockTreeSpec \
  -bufferList {CLKBUFX1 CLKBUFX12 CLKBUFX16 CLKBUFX2 CLKBUFX20 CLKBUFX3 CLKBUFX4 CLKBUFX8 CLKBUFXL CLKINVX1 CLKINVX12 CLKINVX16 CLKINVX2 CLKINVX20 CLKINVX3 CLKINVX4 CLKINVX8 CLKINVXL} \
  -file param/Clock.ctstch;#bufferList depends on the tech you use
clockDesign -specFile param/Clock.ctstch \
  -outDir report/cts_report -fixedInstBeforeCTS
deleteTrialRoute

#------------------------------------------
# Save
#------------------------------------------

saveDesign dbs/pr_cts.enc -compress

2.3.7. 第六步：PR-Post CTS

set TOP_NAME xxx
restoreDesign dbs/pr_cts.enc.dat $TOP_NAME

setDrawView place

#------------------------------------------
# ECO postCTS
#------------------------------------------

setOptMode -fixCap true -fixTran true -fixFanoutLoad true
optDesign -postCTS -outDir report/ECO_post_CTS
optDesign -postCTS -incr -outDir report/ECO_post_CTS_incr
deleteTrialRoute

#------------------------------------------
# Place tie hi/lo cell
#------------------------------------------

setTieHiLoMode -reset
setTieHiLoMode -cell {  TIEHI TIELO } \
  -maxDistance 100 \
  -maxFanOut 10 \
  -honorDontTouch false \
  -createHierPort false
addTieHiLo -cell {TIEHI TIELO} -prefix LTIE
### Tie cell name depends on the tech you use.
### Prefix can be any string you want.
deleteTrialRoute

#------------------------------------------
# Save
#------------------------------------------

saveDesign dbs/pr_post.enc -compress

2.3.8. 第七步：PR-Nano route

set TOP_NAME xxx
restoreDesign dbs/pr_post.enc.dat $TOP_NAME

setDrawView place

#------------------------------------------
# First: route design
#------------------------------------------

setEndCapMode -reset
setEndCapMode -boundary_tap false
setUsefulSkewMode -maxSkew false \
  -noBoundary false \
  -useCells {BUFX1 BUFX12 BUFX16 BUFX2 BUFX20 BUFX3 BUFX4 BUFX8 CLKBUFX12 CLKBUFX16 CLKBUFX2 CLKBUFX20 CLKBUFX3 CLKBUFX4 CLKBUFX8 DLY1X1 DLY2X1 DLY3X1 DLY4X1 CLKINVX12 CLKINVX16 CLKINVX2 CLKINVX20 CLKINVX3 CLKINVX4 CLKINVX8 INVX1 INVX12 INVX16 INVX2 INVX20 INVX4 INVX8 INVXL} \
  -maxAllowedDelay 1
setTieHiLoMode -reset
setTieHiLoMode -cell {TIEHI TIELO} \
  -maxDistance 100 \
  -maxFanOut 10 \
  -honorDontTouch false \
  -createHierPort false
### Set top routing layer
setNanoRouteMode -quiet -routeTopRoutingLayer 5
setNanoRouteMode -quiet -timingEngine {}
setNanoRouteMode -quiet -routeWithSiPostRouteFix 0
### Set bottom routing layer
setNanoRouteMode -quiet -routeBottomRoutingLayer default
setNanoRouteMode -quiet -drouteEndIteration default
setNanoRouteMode -quiet -routeWithTimingDriven false
setNanoRouteMode -quiet -routeWithSiDriven false
setNanoRouteMode -quiet -drouteFixAntenna 1
routeDesign -globalDetail -placementCheck

#------------------------------------------
# Second: eco design, fix antenna
#------------------------------------------
setAnalysisMode -analysisType onChipVariation -cppr both
setNanoRouteMode -quiet -drouteFixAntenna 1
editDeleteViolations
ecoRoute

#------------------------------------------
# Save
#------------------------------------------

saveDesign dbs/pr_route.enc -compress

需要说明的是：这里routing时可以指定底层和顶层金属，但是这个指定不具有约束性。

比如我定义top布线金属是MET5，但是通过布线试验，发现某个区域依然走不通，那么Innovus还是会启用MET6，以走通为第一目标。

如果真的需要严格的关于禁止布线的限制，应该在Flooplan时做Create Route Blockage，可以严格限定禁止使用某层金属。

2.3.9. 第八步：PR-Signoff

set TOP_NAME xxx
restoreDesign dbs/pr_route.enc.dat $TOP_NAME

setDrawView place

#------------------------------------------
# ECO post route
#------------------------------------------

setOptMode -fixCap true -fixTran true -fixFanoutLoad true
optDesign -postRoute -outDir report/ECO_post_route
optDesign -postRoute -incr -outDir report/ECO_post_route_incr
deleteTrialRoute

#------------------------------------------
# Add Filler
#------------------------------------------

getFillerMode -quiet
addFiller -cell FILL1 FILL16 FILL2 FILL32 FILL4 FILL64 FILL8 \
  -prefix FILLER -doDRC
### Filler cell list depends on the tech you use

#------------------------------------------
# Metal fill
#------------------------------------------

# delete existing fill
deleteMetalFill -layer { METAL1 METAL2 METAL3 METAL4 METAL5 METAL6 }

# setup fill
getCTSMode -engine -quiet
setMetalFill -layer METAL1 -opcActiveSpacing 0.230
setMetalFill -layer METAL2 -opcActiveSpacing 0.280
setMetalFill -layer METAL3 -opcActiveSpacing 0.280
setMetalFill -layer METAL4 -opcActiveSpacing 0.280
setMetalFill -layer METAL5 -opcActiveSpacing 0.280
setMetalFill -layer METAL6 -opcActiveSpacing 0.460

# do fill
addMetalFill -layer { METAL1 METAL2 METAL3 METAL4 METAL5 } \
  -nets { VSS VDD } \
  -removeFloatingFill

#------------------------------------------
# Save
#------------------------------------------

saveDesign dbs/pr.enc -compress

2.3.10. 第九步：检查并输出文件

### Output files
set TOP_NAME xxx
restoreDesign dbs/pr.enc.dat $TOP_NAME

# Clear DRC markers in violation browser
#  before final verification
clearDrc

#------------------------------------------
# Verify Geometry
#------------------------------------------

setVerifyGeometryMode -area { 0 0 0 0 } \
  -minWidth true -minSpacing true \
  -minArea true -sameNet true \
  -short true -overlap false \
  -offRGrid false -offMGrid true \
  -mergedMGridCheck true \
  -minHole true -implantCheck true \
  -minimumCut true -minStep true \
  -viaEnclosure true -antenna false \
  -insuffMetalOverlap true -pinInBlkg false \
  -diffCellViol true -sameCellViol false -padFillerCellsOverlap true \
  -routingBlkgPinOverlap true \
  -routingCellBlkgOverlap true \
  -regRoutingOnly false \
  -stackedViasOnRegNet false \
  -wireExt true -useNonDefaultSpacing false \
  -maxWidth true -maxNonPrefLength -1 \
  -error 1000

verifyGeometry

#------------------------------------------
# Verify Geometry
#------------------------------------------

verifyConnectivity -type all -error 1000 -warning 50

#------------------------------------------
# Write output file
#------------------------------------------

# write gdsii
streamOut output/${TOP_NAME}.gds \
  -mapFile map/streamOut.map.gdl \
  -libName DesignLib -units 2000 -mode ALL

# write no power netlist
remove_assigns
deleteEmptyModule
saveNetlist output/${TOP_NAME}_power.v -includePowerGround -flat

# write power netlist
saveNetlist output/${TOP_NAME}_nopow.v -flat;# Flatten, for design
saveNetlist output/${TOP_NAME}_apr.v;# Not flatten, for simulation

# write sdf
all_hold_analysis_views 
all_setup_analysis_views 
write_sdf  -ideal_clock_network output/${TOP_NAME}_apr.sdf

# save design
saveDesign dbs/signoff.enc -compress

Verify Geometry和Verify Connectivity的参数很多不太好在脚本中修改，而且如果有错，在GUI中通过Violation Browser检查是更好的方法。所以这两步完全可以不写进脚本里，用GUI操作进行。

2.4. 总结

以上就是所有的脚本。

写脚本的基本方法是：

  • 按照操作顺序在GUI中操作，找出对应的tcl命令并放到脚本里。
  • 对于一些难以用GUI完成的操作，在tcl中查找命令、查找帮助，写进脚本里。

如果需要查找某个命令的参数，在命令行中输入<command> -help可以查看。

如果只是想找某个功能但是不知道叫什么，可以尝试搜索，输入help <command>，配合通配符*可以快速查找相关命令，一般命令都是全拼的。但是这个有时候也不靠谱（比如三种Blockage的命令命名规则都不一样，有点坑）。

以上脚本只能完成比较规范、简单的数字模块，要求尺寸是方形，没有奇怪的切割、分区等等，更复杂的功能有待探索和开发。

posted @ 2024-06-26 19:57  白发戴花君莫笑  阅读(1036)  评论(0)  编辑  收藏  举报