booth乘法

booth乘法节省面积、速度较移位相加速度也更快。

一个例子：14乘以-5，乘数和被乘数都用5bit补码表示，结果有10bit表示。

14的补码:01110, -5的补码11011 ，正确结果为-70：11 1011 1010

使用一个状态机实现这个乘法，IDLE下初始化等待数据输入，再进行加法和移位，次数由输入位宽决定，最后数据输出。

程序代码如下：

// **************************************************************


// File name     :  booth.v
// Module name  :  BOOTH
// Full name     :   multiply based on booth's algorithm
//
// Author        :  Yang Li
// Email         :  yangli0534@gmail.com
// Date          :   2013/11/24
// Version       :  V 1.0
//
//Abstract        : an implementation of multiplier based on booth's algorithm
 // multiplier ,multiplicand :2's complement
//
// Modification history
// ------------------------------------------------------------------------------------------------------

// *********************************************************************

 module booth
 #(parameter WIDTH =8 )
 (

     input wire             sys_clk,
      input wire             sys_rst_n,
      input wire [WIDTH-1:0] multiplicand,
      input wire [WIDTH-1:0] multiplier,
      input wire             data_av,
      output reg            rfd,
      output reg            rdy,
      output reg [2*WIDTH-1:0] product,
      output reg [2*WIDTH-1:0] product_r
 );
 //*********************
//parameter DECLARATION
//*********************
 localparam [3:0] IDLE  = 4'b0001,
                  ADD   = 4'b0010,
                      // TAP   = 5'b00100,
                       SHIFT = 4'b0100,
                       DONE  = 4'b1000;

 //localparam N= log2(WIDTH) ;
 localparam N=5;
 localparam WIDTH_PROD = 2*WIDTH;
//*********************
//INNER SIGNAL DECLARATION
//*********************
 reg [WIDTH-1:0] multiplicand_add, multiplicand_minus;//鍔犺涔樻暟锛屽噺琚箻鏁
 reg [WIDTH-1:0] upper_r, lower_r;//楂樺崐鍜屼綆鍗
 reg booth_r;  //booth bit
 reg [3:0] state_curr, state_next;
 reg [N-1:0] cnt_r;//

 reg [WIDTH-1:0] upper, lower;//楂樺崐鍜屼綆鍗
 reg booth;  //booth bit
 reg [N-1:0] cnt;//
  //reg [WIDTH_PROD-1:0] product;

 always @(posedge sys_clk or negedge sys_rst_n)
 begin: MULTIPLICAND
     if(!sys_rst_n)
          begin
                multiplicand_add <= 0;
                 multiplicand_minus <= 0;
            end
     else if(rfd)
          begin
                multiplicand_add <= multiplicand;
                 multiplicand_minus <= ~multiplicand + 1'b1;
           end
 end

 always @(posedge sys_clk or negedge sys_rst_n)
 begin: STATE_CTRL
     if(!sys_rst_n) begin
          state_curr <= IDLE;
            upper_r <= 0;
            lower_r <= 0;
            booth_r <=0;
            cnt_r <= 0;
            end
      else begin
           state_curr <= state_next;
            upper_r <= upper;
            lower_r <= lower;
            booth_r <= booth;
            cnt_r <= cnt;
           end
 end

 always @(*)
 begin:STATE_NEXT
      state_next = state_curr;
     case(state_curr)
         IDLE: begin
                if(data_av)
                     state_next = ADD;
            end
           ADD:
                state_next = SHIFT;
          // TAP:
        //     state_next = SHIFT;
            SHIFT: begin
                if(cnt_r==WIDTH)
                     state_next = DONE;
                 else
                     state_next = ADD;
            end
            DONE:
                state_next = IDLE;

            default: state_next = IDLE;
     endcase

 end

 always @*
 begin: OUT
     rfd  = 1'b0;
      rdy  = 1'b0;
      product  = 0;
      cnt  = cnt_r;
      upper  = upper_r;
      lower  = lower_r;
      booth =booth_r;
     case(state_curr)
      IDLE: begin
          rfd  = 1'b1;
            cnt = 0;
            upper = 0;
            booth = 1'b0;
            if(data_av)
                lower  = multiplier;
      end
      ADD: begin
          cnt = cnt_r + 1'b1;
          case({lower_r[0],booth_r})
               2'b00:  upper  = upper_r;
                2'b01:  upper  = upper_r + multiplicand_add;
                2'b10:  upper  = upper_r + multiplicand_minus;
                2'b11:  upper  = upper_r;

            endcase
      end
      //TAP: begin

     // end

      SHIFT: begin


                 upper  = {upper_r[WIDTH-1],upper_r[WIDTH-1:1]};
                 lower  = {upper_r[0],lower_r[WIDTH-1:1]};
                 booth  = lower_r[0];

      end

      DONE: begin
            product ={upper_r, lower_r};
              rdy = 1'b1;
      end
      endcase

 end

  always @(posedge sys_clk or negedge sys_rst_n)
  begin: register
  if(!sys_rst_n)
     product_r <= 0;
  else if(rdy)
     product_r <= product;
  end

 endmodule

仿真结果

 
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