I.MX51 IOMUX
The IOMUX controller contains four sets of registers that affect the i.MX53 registers, as follows:
• General-purpose registers (IOMUXC_GPRx)—consist of three registers that control PLL
frequency, voltage, and other general purpose sets.
• “Daisy Chain” control registers (IOMUXC_<Instance_port>_SELECT_INPUT)—control the
input path to a module when more than one pad may drive the module’s input
• MUX control registers (changing pad modes):
— Select which of the pad’s 8 different functions (also called ALT modes) is used.
— Can set pad’s functions individually or by group using one of the following registers:
– IOMUXC_SW_MUX_CTL_PAD_<PAD NAME>
– IOMUXC_SW_MUX_CTL_GRP_<GROUP NAME>
• Pad control registers (changing pad characteristics):
— Set pad characteristics individually or by group using one of the following registers:
– IOMUXC_SW_PAD_CTL_PAD_<PAD_NAME>
– IOMUXC_SW_PAD_CTL_GRP_<GROUP NAME>
— Pad characteristics are:
– SRE (1 bit slew rate control)—Slew rate control bit; selects between FAST/SLOW slew rate
output. Fast slew rate is used for high frequency designs.
– DSE (2 bits drive strength control)—Drive strength control bits; select the drive strength
(low, medium, high, or max).
– ODE (1 bit open drain control)—Open drain enable bit; selects open drain or CMOS output.
– HYS (1 bit hysteresis control)—Selects between CMOS or Schmitt Trigger when pad is an
input.
PUS (2 bits pull up/down configuration value)—Selects between pull up or down and its
value.
– PUE (1 bit pull/keep select)—Selects between pull up or keeper. A keeper circuit help assure
that a pin stays in the last logic state when the pin is no longer being driven.
– PKE (1 bit enable/disable pull up, pull down or keeper capability)—Enable or disable pull
up, pull down, or keeper.
– DDR_MODE_SEL (1 bit ddr_mode control)—Needed when interfacing DDR memories.
– DDR_INPUT (1 bit ddr_input control)—Needed when interfacing DDR memories.
Setting Up the IOMUXC and U-Boot
To setup the IOMUXC and configure the pads on U-Boot, use the four files described in Table 13-1:
Defining the Pads
The iomux.c file contains each pad’s IOMUXC definitions. Use the following code to see the default
definitions:
enum iomux_pins {
...
...
...
MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
...
...
...
}
To change the values for each pad according to your hardware configuration, use the following:
MX53_PIN_<PIN NAME> = _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi)
Where:
• gp—IO Pin
• gi—IO Instance
• ga—MUX Mode
• mi—MUX Control Offset
• pi—PAD Control Offset
Configuring IOMUX Pins for Initialization Function
The mx53<reference board name>.c file contains the initialization functions for all peripherals (such as
UART, I2C, and Ethernet). Configure the relevant pins for each initializing function, using the following:
mxc_request_iomux(<pin name>, <iomux config>);
mxc_iomux_set_input(<mux input select>, <mux input config>);
mxc_iomux_set_pad(<pin name>, <iomux pad config>);
Where the following applies:
<pin name> See all pins definitions on file mx53_pins.h
<iomux config> See parameters defined at iomux_config enumeration on file iomux.h
<iomux input select> See parameters defined at iomux_input_select enumeration on file iomux.h
<iomux input config> See parameters defined at iomux_input_config enumeration on file iomux.h
<iomux pad config> See parameters defined at iomux_pad_config enumeration on file iomux.h
Example—Setting a GPIO
For an example, configure and use pin PATA_DA_1 (PIN L3) as a general GPIO and toggle its signal.
Add the following code to the file mx53_<reference board name>.c, function board_init:
1 // Request ownership for an IO pin.
2 mxc_request_iomux(MX53_PIN_ATA_DA_1, IOMUX_CONFIG_ALT1);
3 // Set pin as 0
4 reg = readl(GPIO7_BASE_ADDR + 0x0);
5 reg &= ~0x80;
6 writel(reg, GPIO7_BASE_ADDR + 0x0);
7 // Set pin direction as output
8 reg = readl(GPIO7_BASE_ADDR + 0x4);
9 reg |= 0x80;
10 writel(reg, GPIO7_BASE_ADDR + 0x4);
11 // Delay 0.5 seconds
12 udelay(500000);
13 // Set pin as 1
14 reg = readl(GPIO7_BASE_ADDR + 0x0);
15 reg |= 0x80;
16 writel(reg, GPIO7_BASE_ADDR + 0x0);
17 // Delay 0.5 seconds
18 udelay(500000);
19 // Set pin as 0
20 reg = readl(GPIO7_BASE_ADDR + 0x0);
21 reg &= ~0x80;
22 writel(reg, GPIO7_BASE_ADDR + 0x0);
Setting Up the IOMUXC in Linux
The folder linux/arch/arm/mach-<platform name> contains the specific machine layer file for your custom
board. For example, the machine layer file used on the i.MX53 <reference> boards are
linux/arch/arm/mach-mx5/mx53_<reference board name>.c. This platform is used in the examples in this
section. The machine layer files include the IOMUX configuration information for peripherals used on a
specific board.
IOMUX Configuration Definition
The iomux-mx53.h file contains definitions for all i.MX53 pins. Pin names are formed according to the
formula <SoC>PAD<Pad Name>_GPIO<Instance name>_<Port name>. Definitions are created with the
following line code.
IOMUX_PAD(PAD Control Offset, MUX Control Offset, MUX Mode, Select Input Offset, Select Input,
Pad Control)
The variables are defined as follows:
PAD Control Offset Address offset to pad control register
(IOMUXC_SW_PAD_CTL_PAD_<PAD_NAME>)
MUX Control Offset Address offset to MUX control register
(IOMUXC_SW_MUX_CTL_PAD_<PAD NAME>)
MUX Mode MUX mode data, defined on MUX control registers
Select Input Offset Address offset to MUX control register
(IOMUXC_<Instance_port>_SELECT_INPUT)
Select Input Select Input data, defined on select input registers
Pad Control Pad Control data, defined on Pad control registers
Definitions can be added or changed, as shown in the following example code:
#define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD (0x620, 0x2A0, 4, 0x888, 3,
MX53_UART_PAD_CTRL)
The variables are as follows:
• 0x620—PAD Control Offset
• 0x2A0—MUX Control Offset
• 4—MUX Mode
• 0x888—Select Input Offset
• 3—Select Input
• MX53_UART_PAD_CTRL—Pad Control
For all addresses and register values, check the IOMUX chapter in the i.MX53 Applications Processor
Reference Manual.
