# Design Constraint by DC
# variables
set CLK_SPEED 125
set CLK_PERIOD 1000/125
set INCLK_PERIOD 3.2
set OUTCLK_PERIOD 3.2
set OPER_COND slow_125_1.62
set WIRE_LOAD 40KGATES
set CELL_DRIVING_IN inv1a1
set MAX_CAP_NUM 10
set MAX_CAP_NAME buf1a1/A
set NUM_DRIVEN_OUT 4
set SYSCLK CLK
set TECHLIB myLib
# script
reset_design
set all_in_ex_clk [remove_form_collection [all_inputs] [get_ports $SYSCLK]]
create_clock -name sysclk -period $CLK_PERIOD [get_ports $SYSCLK]
set_input_delay -max $CLK_PERIOD-$INCLK_PERIOD -clock sysclk $all_in_ex_clk
set_output_delay -max $CLK_PERIOD-$OUTCLK_PERIOD -clock sysclk $all_in_ex_clk
set_operating_condition -max $OPER_COND
set_wire_load_model -name $WIRE_LOAD
set_driving_cell -lib_cell $CELL_DRIVING_IN $all_in_ex_clk
set MAX_LOAD [expr [load_of $TECHLIB/$MAX_CAP_NAME ] * $MAX_CAP_NUM]
set_max_load -max $MAX_LOAD $all_in_ex_clk
set_load [expr $MAX_LOAD * $NUM_DRIVEN_OUT] [all_outputs]
