1 //电子表的设计包括正常计时模块，LED显示模块，定时报警模块，校时模块，秒表模块。
2 //（1）正常计时模块clock
3 module clock(clk,rst,clock_en,second,minute,hour);
4 input clk,rst,clock_en;
5 output[5:0]second,minute,hour;
6 reg[5:0]second,minute,hour;
7 always@(posedge clk or negedge rst or posedge clock_en)
8 if(!rst)
9 begin
10 second<=0; minute<=0; hour<=0;
11 end
12 else if(clock_en)
13 begin
14 if(second==59)
15 begin
16 minute<=minute+1;
17 second<=0;
18 end
19 else if(minute==59)
20 begin
21 hour<=hour+1;
22 minute<=0;
23 end
24 else if(hour==23)
25 hour<=0;
26 else
27 second<=second+1;
28 end
29 endmodule
30 //(2)LED显示模块LED_display
31 module LED_display(data,high,low);
32 input[5:0]data;
33 output[7:0]high,low;
34 reg[7:0]high,low;
35 reg[3:0]out_h,out_l;
36 always@(data)
37 begin
38 out_h<=data/10;
39 out_l<=data;
40 end
41 always@(out_l)
42 case(out_l)
43 4'b0000:low<=8'b00000000;
44 4'b0001:low<=8'b01100000;
45 4'b0010:low<=8'b11011010;
46 4'b0011:low<=8'b11110010;
47 4'b0100:low<=8'b01100110;
48 4'b0101:low<=8'b10110110;
49 4'b0110:low<=8'b10111110;
50 4'b0111:low<=8'b11100000;
51 4'b1000:low<=8'b11111110;
52 4'b1001:low<=8'b11110110;
53 default:low<=8'b00000000;
54 endcase
55
56 always@(out_h)
57 case(out_h)
58 4'b0000:high<=8'b00000000;
59 4'b0001:high<=8'b01100000;
60 4'b0010:high<=8'b11011010;
61 4'b0011:high<=8'b11110010;
62 4'b0100:high<=8'b01100110;
63 4'b0101:high<=8'b10110110;
64 4'b0110:high<=8'b10111110;
65 4'b0111:high<=8'b11100000;
66 4'b1000:high<=8'b11111110;
67 4'b1001:high<=8'b11110110;
68 default:high<=8'b00000000;
69 endcase
70 endmodule
71 //（3）定时模块timing和报警模块alarm
72 module timing(rst,timing_en,hour,minute,hour,location_adjust,timing_adjust,hour_timing,minute_timing,secong_timing,out);
73 input rst,timing_en,location_adjust;
74 input[5:0]minute,hour,second;
75 output[5:0]second_timing,minute_timing,hour_timing;
76 reg[5:0]second_timing,minute_timing,hour_timing;
77 output out;
78 reg[1:0]location
79 always@（negedge rst or posedge timing_en or posedge location_adjust)
80 if(!rst)
81 begin
82 second_timing<=0; minute_timing<=0; hour_timing<=0;location<=0;
83 end
84 else if(location_adjust==1)
85 begin
86 if(location==2'b10)
87 location<=2'b00;
88 else
89 location<=location+1;
90 end
91 else if(timing_en==1)
92 begin
93 if(location==2'b00)
94 hour_timing<=hour_timing+1;
95 else if(location==2'b01)
96 minute_timing<=minute_timing+1;
97 else if(location==2'b10)
98 second_timing<=second_timing+1;
99 else
100 begin
101 second_timing<=second_timing;
102 minute_timing<=minute_timing;
103 hour_timing<=hour_timing;
104 end
105 end
106 assign out=(hour_timing==hour && minute_timing==minute && second_timing==second)?1:0;
107 endmodule
108
109 //报警模块alarm
110 module alarm(clk,rst,alarm_en,alarm_out);
111 input clk,rst,alarm_en;
112 output alarm_out;
113 reg alarm_out;
114 reg[4:0] count;
115 always@(posedge clk or negedge rst)
116 if(!rst)
117 begin
118 alarm_out<=0;
119 count<=0;
120 end
121 else if(alarm_en==1)
122 begin
123 if(count==29)
124 begin
125 count<=0;
126 alarm_out<=0;
127 end
128 else
129 begin
130 count<=count+1;
131 alarm_out<=1;
132 end
133 end
134 else
135 begin
136 count<=0;
137 alarm_out<=0;
138 end
139 endmodule
140 (4)校时模块adjust_time
141 module adjust_time(rst,adjust_en,location_adjust,second,minute,hour,second_adjust,minute_adjust,hour_adjust);
142 input rst,adjust_en,location_adjust;
143 input[5:0]second,minute,hour;
144 output[5:0]second_adjust,minute_adjust,hour_adjust;
145 reg[5:0]second_adjust,minute_adjust,hour_adjust;
146 reg[1:0]location
147
148 always@(posedge adjust_en or location_adjust or negedge rst)
149 if(!rst)
150 begin
151 second_adjust<=0;minute_adjust<=0;hour_adjust<=0;location<=0;
152 end
153 else if(location_adjust)
154 begin
155 if(location==2'b10)
156 location<=2'b00;
157 else
158 location<=location+1;
159 end
160 else if(adjust_en==1)
161 begin
162 case(location)
163 2'b00: hour_adjust<=hour_adjust+1;
164 2'b01: minute_adjust<=minute_adjust+1;
165 2'b10: second_adjust<=second_adjust+1;
166 default:
167 begin
168 hour_adjust<=0;
169 minute_adjust<=0;
170 second_adjust<=0;
171 end
172 endcase
173 end
174 endmodule
175 //(5)秒表模块second_watch
176 module second_watch(clk,rst,watch_en,stop,minute,second);
177 input clk,rst,watch_en,stop;
178 output[5:0]minute,second;
179 reg[9:0]dout;
180 always(posedge clk or negedge rst)
181 if(!rst)
182 dout<=0;
183 else if(watch_en)
184 begin
185 if(stop==1)
186 dout<=dout;
187 else if(dout==999&&stop==1)
188 dout<=0;
189 else
190 dout<=dout+1;
191 end
192 assign minute=dout/60;
193 assign second=dout`;
194 endmodule
195// (6)计时，报警，校时，秒表状态的转换
196 module state(clk,rst,c0,c1,c2,c3,clock_en,timing_en,adjust_en,watch_en);
197
198 input clk,rst,c0,c1,c2,c3;
199 output clock_en,timing_en,adjust_en,watch_en;
200 reg clock_en,timing_en,adjust_en,watch_en;
201 reg[3:0]state,next_state;
202 parameter s0=4'b0000,s1=4'b0001,s2=4'b0010,s3=4'b0011;
203
204 always@(posedge clk)
205 if(!rst)
206 state<=s0;
207 else
208 state<=next_state;
209
210 always@(state or rst or c0 or c1 or c2 or c3)
211 begin
212 if(!rst)
213 next_state<=s0;
214 else
215 begin
216 case(state)
217 s0: begin
218 if(c1)
219 next_state<=s1;
220 else if(c2)
221 next_state<=s2;
222 else if(c3)
223 next_state<=s3;
224 else
225 next_state<=s0;
226 end
227 s1: begin
228 if(c1)
229 next_state<=s1;
230 else if(c2)
231 next_state<=s2;
232 else if(c3)
233 next_state<=s3;
234 else
235 next_state<=s0;
236 end
237 s2: begin
238 if(c1)
239 next_state<=s1;
240 else if(c2)
241 next_state<=s2;
242 else if(c3)
243 next_state<=s3;
244 else
245 next_state<=s0;
246 end
247 s3: begin
248 if(c1)
249 next_state<=s1;
250 else if(c2)
251 next_state<=s2;
252 else if(c3)
253 next_state<=s3;
254 else
255 next_state<=s0;
256 end
257 default:next_state<=s0;
258 endcase
259 end
260 end
261
262 always@(state)
263 begin
264 case(state)
265 s0: begin （计时）
266 clock_en<=1;
267 timing_en<=0;
268 adjust_en<=0;
269 watch_en<=0;
270 end
271 s1: begin（定时报警）
272 clock_en<=1;
273 timing_en<=1;
274 adjust_en<=0;
275 watch_en<=0;
276 end
277 s2: begin（校时）
278 clock_en<=0;
279 timing_en<=0;
280 adjust_en<=1;
281 watch_en<=0;
282 end
283 s3: begin（秒表）
284 clock_en<=1;
285 timing_en<=0;
286 adjust_en<=0;
287 watch_en<=1;
288 end
289 default:begin
290 clock_en<=1;
291 timing_en<=0;
292 adjust_en<=0;
293 watch_en<=0;
294 end
295 endcase
296 end
297 endmodule
298 // （7）电子表顶层模块dianzibiao_top
299 //`include"adjust_time.v"
300 //`include"alarm.v"
301 //`include"clock.v"
302 //`include"LED_display.v"
303 //`include"second_watch.v"
304 //`include"state.v"
305 //`include"timing.v"
306 //`include"top.v"
307 module dianzibiao_top( clk,rst,c0,c1,c2,c3,stop,location,hour_h,hour_l,minute_h,minute_l,second_h,second_l,alarm_out);
308
309 input clk,rst,c0,c1,c2,c3,stop,location;
310 output[7:0]hour_h,hour_l,minute_h,minute_l,second_h,second_l;
311 output alarm_out;
312 wire[5:0]second,minute,hour,second_clock,minute_clock,hour_clock,hour_LED,minute_LED,second_LED,sec_timing,min_timing,hour_timing,sec_adjust,min_adjust,hour_adjust,minute_adjust,second_adjust;
313 wire clock_en,alarm_en,timing_en,adjust_en,watch_en;
314 wire[5:0]minute_w,second_w;
315
316 clock clock1(.second(second_clock),.minute(minute_clock),.hour(hour_clock),.clock_en(clock_en),.clk(clk),.rst(rst));
317
318 LED_display LED_display1(.data(hour_LED),.high(hour_h),.low(hour_l));
319 LED_display LED_display2(.data(minute_LED),.high(minute_h),.low(minute_l));
320 LED_display LED_display3(.data(second_LED),.high(second_h),.low(second_l));
321
322 alarm alarm1(.alarm_out(alarm_out),.alarm_en(alarm_en),.clk(clk),.rst(rst));
323
324 timing timing1(.rst(rst),.timing_en(timing_en),.location_adjust(location),.hour(hour_clock),.minute(minute_clock),.second(second_clock),.second_timing(sec_timing),.minute_timing(min_timing),.hour_timing(hour_timing),.out(alarm_en));
325
326 adjust_time adjust_time1(.rst(rst),.adjust_en(adjust_en),.location_adjust(location),.hour(hour_clock),.minute(minute_clock),.second(second_clock),.second_adjust(sec_adjust),.minute_adjust(min_adjust),.hour_adjust(hour_adjust));
327
328 second_watch second_watch1(.watch_en(watch_en),.clk(clk),.rst(rst),.stop(stop),.minute(minute_w),.second(second_w));
329
330 state state1(.clk(clk),.rst(rst),.c0(c0),.c1(c1),.c2(c2),.c3(c3),.clock_en(clock_en),.timing_en(timing_en),.adjust_en(adjust_en),.watch_en(watch_en));
331
332 assign hour=c1?hour_timing:hour_clock;
333 assign minute=c1?min_timing:minute_clock;
334 assign second=c1?sec_timing:second_clock;
335 assign minute=c3?minute_w:minute_clock;
336 assign second=c3?second_w:second_clock;
337 assign hour=c2?hour_adjust:hour_clock;
338 assign minute=c2?min_adjust:minute_clock;
339 assign second=c2?sec_adjust:second_clock;
340 assign hour_LED=hour;
341 assign minute_LED=minute;
342 assign second_LED=second;
343
344 endmodule
